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fn8760 rev.3.00 nov 8, 2017 zl8802 dual channel/dual phase pmbus chargemode control dc/dc digital controller datasheet fn8760 rev.3.00 page 1 of 91 nov 8, 2017 the zl8802 is a dual output or dual phase digital dc/dc controller. each output can oper ate independently or be used together in a dual phase co nfiguration for high current applications supporting 2-, 4-, 6-, and 8-phase operation with up to four zl8802 controllers. the zl8802 supports a wide range of output voltages (0.54v to 5.5v) operating from input voltages as low as 4.5v up to 14v. with the fully digital chargemo de control, the zl8802 will respond to a transient load step within a single switching cycle. this unique compensation-free modulation technique allows designs to meet transient specif ications with minimum output capacitance, thus saving cost and board space. the proprietary single-wire di gital-dc? (ddc) serial bus enables the zl8802 to communicate between other intersil digital power ics. by using the ddc, the zl8802 achieves complex functions such as inter-ic phase current balancing, sequencing, and fault spreading. this eliminates complicated power supply managers with numerous external discrete components. the zl8802 features fast output overcurrent protection. the input voltage, output voltag es, and drmos/mosfet driver supply voltages are overvoltag e and undervoltage protected. two external temperature sensors and one internal temperature sensor are available for temperature monitoring, one of which can be configured for under- and over- temperature protection. a snapshot parametric capture feature allows users to take a snapshot of operating and fault data during normal or fault conditions. integrated low dropout (ldo) regulators allow the zl8802 to operate from a single input supply eliminating the need for additional linear regulators. th e vdrv ldo output can be used to power external drivers or drmos devices. with full pmbus compliance, the zl8802 is capable of measuring and reporting input vo ltage, input current, output voltage, output current, as well as the device?s internal temperature, two external temperatures, and an auxiliary voltage or temperature input. features ? unique compensation-free design ? always stable ? output voltage range: 0.54v to 5.5v ? input voltage range: 4.5v to 14v ? 1% output voltage accuracy over line, load, and temperature ? chargemode control achieves fast transient response, reduced output capacitance, and provides output stability without compensation. ? 2-channel output, 2-, 4-, 6-, or 8-phase output with two, three, or four devices ? switching frequency range 200khz to 1.33mhz ? proprietary single-wire ddc (digital-dc) serial bus enables voltage sequencing and fault spreading with other intersil digital power ics ? inductor peak and averaged over and undercurrent protection ? digital fault protection for output voltage uv/ov, input voltage uv/ov, temperature, and mosfet driver voltage ? accurate average output current measurement with adjustable gain settings fo r sensing with sps current monitor outputs or high current, low dcr inductors ? monitor adc measures input voltage, input current, output voltage, driver voltage, inte rnal and external temperature ? nonvolatile memory for storing operating parameters and fault events ? pmbus compliant applications ? servers and storage equipment ? telecom and datacom equipment ? power supplies (memory, dsp, asic, fpga) related literature ? for a full list of related documents, visit our website - zl8802 product page table 1. key differences between family of parts part number dual output dual phase ddc current share sps support zl8800 yes yes no no zl8801 no yes yes no zl8802 yes yes yes yes
zl8802 fn8760 rev.3.00 page 2 of 91 nov 8, 2017 table of contents two-phase application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 zl8802 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 digital-dc architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin-strap pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 configurable pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 smbus device address selection (sa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output voltage and vout_max selection (vset0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 switching frequency setting (sync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 input voltage undervoltage lockout setting (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 configuration setting (cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chargemode control (ascr) setting (ascrcfg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 start-up and shutdown settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 internal bias regulators and input supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ton-delay and rise times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 enable pin operation and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power management functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output prebias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 current limit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 input current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 external voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 smbus communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 active current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 temperature monitoring using xtemp pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 nonvolatile memory and security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 monitoring through smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pmbus command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pmbus use guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pmbus data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pmbus command detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 mfr_smbalert_mask (dbh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
fn8760 rev.3.00 page 3 of 91 nov 8, 2017 zl8802 two-phase application figure 1. two-ph ase application 9287 =/ 3:0 3:0 9,1 9'' 6'$ 6&/ 3* (1 6*1' '*1' 7021 9'59 ''& 9'59 ,6(1$ ,6(1% ,6(1$ ,6(1% ,17(5'(9,&( &225',1$7,21 237,21$/ 30%86 237,21$/ &21752/$1' 67$786 ?) ?) [?) [?) 6<1& 96(11 96(13 ?) ?) 9 9 9 6$ 96(7 89/2 p? 237,21$/ ,,13 ,,11 6<1& n? 9 ,6/% 9,1 3*1' %227 39&& 3+$6( 9&& &*1' 96:+ 3:0 7021 ?) 5(),1 ,021 9,1 3*1' %227 39&& 3+$6( 9&& &*1' 96:+ 3:0 7021 ?) 5(),1 ,021 ,6/% 96(7 $6&5&)* &)* 9,1
zl8802 fn8760 rev.3.00 page 4 of 91 nov 8, 2017 block diagram sda scl salrt xtemp1p/n sync xtemp0p/n ddc vse t0 vse t1 pwmh0 pwmen0 digital-dc inter-device communications i 2 c and smbus serial interface pin-strap resistor detection sa uvlo microcontroller and nonvolatile memory pll clk gen osc v25 vr5 vr6 ldos pga iinn iinp gain isena1 isenb1 isena0 isenb0 vdrv pga ipeak/iavg adc ipeak/iavg adc vse n0p/n ascr digital pwm modulator pwm+ dead time adc vse n1p/n pwmh1 pwmen1 vmon/tmo n monitor adc mux vdd vdd digital logic + ov/uv/oc/uc comparators pg0/1 en0/1 dac ascr digital pwm modulator pwm+ dead time dac adc vdrven iin adc cfg ascrcfg vtrkp/n pga pga figure 2. block diagram
zl8802 fn8760 rev.3.00 page 5 of 91 nov 8, 2017 pin configuration zl8802 (44 ld qfn) top view (pad) pin description pin #pin name type ( note 1 )description 1scl i/o serial clock. connect to external host and/or to other zl devices. requires a pull-up resistor to a 2.5v to 5.5v (vr5 recommended, do not use v25) source. pull-up su pply must be from an ?always on? source or vr5. 2sda i/o serial data. connect to external host and/or to other zl devices. requires a pull-up resistor to a 2.5v to 5.5v (vr5 recommended, do not use v25) source. pull-up su pply must be from an ?always on? source or vr5. 3salrt o serial alert. connect to external host if desired. requires a pull-up resistor to a 2.5v to 5.5v (recommend vr5, do not use v25) source. leave floating if not used. 4sgndpwr connect to low impedance ground plane. internal connection to sgnd. all pin-strap resistors should be connected to sgnd. sgnd must be connected to dgnd and pgnd using a single point connection. 5sa m serial address select pin. used to assign un ique address for each individual device. see table 3 on page 12 for pmbus address options. connect resistor to sgnd. 6 vmon/ tmon i smart power stage temperature monitoring or general purpose voltage monitoring pin. requires an external 2:1 resistor divider network to correctly read temperatur e. requires an external 16:1 resistor divider network to read voltage. connect bottom of resistor divider network to sgnd. connect vmon/tmon pin to sgnd if not used. 7dgndpwr digital ground. must connect to sgnd and pgnd using a single point connection. 8 ascrcfg m selects chargemode control (ascr) configuration settings. see ? configurable pins ? on page 12 and table 8 on page 14 for details. 9cfg m selects current sense, current limit, and operating mode. see ? configurable pins ? on page 12 and table 8 on page 14 for details. 10 vset0 m channel 0 output voltage selection pin. used to set v out0 and v out0 max. see table 4 on page 12 for v out pin-strap options. default v out max is 115% of v out setting, but this can be overridden through the pmbus interface with the vout_max command. connect resistor to sgnd. 11 vset1 m channel 1 output voltage selection pin. used to set v out1 and v out1 max. see table 4 on page 12 for v out pin-strap options. default v out max is 115% of v out setting, but this can be overridden through the pmbus interface with the vout_max command. connect resistor to sgnd. not used in 2-phase mode. leave fl oating in 2-phase mode. 12 pg0 o channel 0 power-good output. can be configured as open-drain or push-pull using the pmbus interface. default setting is open-drain.
zl8802 fn8760 rev.3.00 page 6 of 91 nov 8, 2017 13 uvlo m undervoltage lockout selection. sets the minimum value for v dd voltage to enable v out . see table 6 on page 13 for uvlo setting options. pin-strapped (configured) values can be over ridden by the pmbus interface. connect resistor to sgnd. if enabling the device by tying the en0 and or en1 pins high (sel f-enabling), set the uvlo level to 16v with a 100k resistor so the device will not turn on until af ter a configuration file has been loaded. 14 ddc i/o single-wire ddc bus (current sharing, interdevice communica tion). requires a pull-up resistor to a 2.5v to 5.5v (recommend vr5, do not use v25) source. pull-up voltage must be present when the device is powered. pull-up supply must be from an ?always on? source or vr5. 15 xtemp0p i external temperature sensor input for channel 0. connect to external 2n3904 (base emitter junction) or equivalent embedded thermal diode. if not used connect to sgnd. 16 xtemp0n i external temperature sensor input for channe l 0 return. if not used connect to sgnd. 17 vtrkp - tracking sense positive input. used to track an external voltag e source. tracking is only poss ible in 2-phase operation, or with a single channel in a 2-channel configuration. tracking is disabled in 4-, 6-, and 8-phase operation. if not used, connect to sgnd. 18 vtrkn - tracking sense negative input (retur n). if not used connect to sgnd. 19 vsen0p i differential output channel 0 voltage sense feedba ck. connect to positive output regulation point. 20 vsen0n i differential output channel 0 voltage sense feedback. connect to negative output regulation point. 21 vdrven i vdrv (mosfet driver bias supply) enable. leave unconnected (float ) or pull up to vr5 to enable, tie to ground to disable. 22 isena0 i positive differential voltage input for channel 0 dcr current sensing. should be routed as a pair with isenb0. should connect to resistor located close to output inductor. see ? sps current sensing ? on page 17 . 23 isenb0 i negative differential voltage input for channel 0 dcr current se nsing. should be routed as a pair with isena0. should be connected to output inductor terminal. see ? sps current sensing ? on page 17 . 24 pwmen0 o used to drive drmos enable where applic able. leave unconnected when not used. 25 pwmh0 o pwm0 high signal. 26 pwmh1 o pwm1 high signal. 27 pwmen1 o used to drive drmos enable where applic able. leave unconnected when not used. 28 isenb1 i negative differential voltage input for channel 1 dcr current se nsing. should be routed as a pair with isena1. should be connected to output inductor terminal. see ? sps current sensing ? on page 17 for details. 29 isena1 i positive differential voltage input for channel 1 dcr current sensing. should be routed as a pair with isenb1. should connect to resistor located close to output inductor. see ? sps current sensing ? on page 17 for details. 30 vdrv pwr mosfet driver bias supply regulator output. if disabled, this pin can be left floating. decoup le with a high quality 4.7f x7r or better ceramic capacito r placed close to this pin. 31 vr6 pwr bypass for internal 6v reference used to power internal circuitry. decouple with a high quality 4.7f x7r or better ceramic capacitor placed close to this pin. ke ep this net as small as possible. do not route near switching signals. 32 vr5 pwr bypass for internal 5v reference used to power internal circuitry. decouple with a high quality 4.7f x7r or better ceramic capacitor placed close to this pin. 33 vdd pwr supply voltage. decouple with a high quality 1f x7r or better ceramic capacitor placed close to this pin. 34 iinn i input current monitor negative input. if not used connect to vdd. 35 iinp i input current monitor positive input. if not used connect to vdd. 36 v25 pwr internal 2.5v reference used to power internal circuitry. deco uple with a high quality 4.7f x7r or better ceramic capacitor placed close to this pin. 37 pg1 o channel 1 power-good output. can be configured as open-drain or push-pull using the pmbus interface. default setting is open-drain. 38 vsen1n i differential output channel 1 voltage sense feedback. connect to negative output regulation point. not used in 2-phase mode. leave floating in 2-phase mode. 39 vsen1p i differential output channel 1 voltage sense feedback. connect to positive output regulation point. not used in 2-phase mode. leave floating in 2-phase mode. 40 xtemp1n i external temperature sensor input for channe l 1 return. if not used connect to sgnd. 41 xtemp1p i external temperature sensor input for channel/phase 1. conn ect to external 2n3904 (base emitter junction) or equivalent embedded thermal diode. if not used connect to sgnd. pin description (continued) pin #pin name type ( note 1 )description
zl8802 fn8760 rev.3.00 page 7 of 91 nov 8, 2017 42 en0 i enable channel 0. active signal enables pwm0 switching. recommended to be tied low during device configuration. refer to ? enable pin operation and timing ? on page 16 for additional information. 43 en1 i enable channel 1. active signal enables pwm1 switching. recommended to be tied low during device configuration. refer to ? enable pin operation and timing ? on page 16 for additional information. not us ed in 2-phase mode. when not used, we recommend connecting this pin to ground. 44 sync m/i/o clock synchronization input. used to set the frequency of the internal clock, to sync to an external clock or to output interna l clock. when configured as an output this pin is push-pull and does not require a pull-up. see ? switching frequency setting (sync) ? on page 12 and table 5 on page 12 for additional information. pad sgnd pwr exposed thermal pad. connect to low impedance ground plane. internal connection to sgnd. note: 1. i = input, o = output, pwr = power or ground, m = multimode pins. pin description (continued) pin #pin name type ( note 1 )description ordering information part number ( notes 2 , 3 , 4 ) part marking temp. range (c) tape and reel quantity (units) package (rohs compliant) pkg. dwg. # zl8802alaft 8802 -40 to +85 4k 44 ld qfn l44.7x7b zl8802alaft7a 8802 -40 to +85 250 44 ld qfn l44.7x7b ZL8802ALAFTK 8802 -40 to +85 1k 44 ld qfn l44.7x7b notes: 2. refer to tb347 for details on reel specifications. 3. these pb-free plastic packaged products employ special pb-free ma terial sets, molding compounds/die attach materials, and 100 % matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), refer to the product information page for the zl8802 . for more information on msl, refer to tb363 . f a a zl8802 t l product designator package designator a = qfn package operating temperature range l = -40c to +85c firmware revision alpha character lead finish f = lead-free matte tin shipping option contact factory for other options t = tape and reel - 4000 pcs
zl8802 fn8760 rev.3.00 page 8 of 91 nov 8, 2017 absolute maximum rating s thermal information dc supply voltage: vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v logic i/o voltage: ddc, en0, en1, pg0, pg1, sa, vdrven, salrt, scl, sda, sync, uvlo, vmon/tmon, vset0, vset1, cfg, ascrcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v analog input voltages: vsen0p, vsen0n, vsen1p, vsen1n, isena0, isena1, isenb0, isenb1 . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v xtemp0p, xtemp1p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v xtemp0n, xtemp1n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v iinn, iinp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v logic reference : v25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v bias supplies: vr5, vr6, vdrv. . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v pwm logic outputs, pwmh0, pwmh1, pwml0, pwml1 . . . .-0.3v to 6.5v ground voltage differential (vdgnd-vsgnd), . . . . . . . . . . . . . . .-0.3v to +0.3v esd ratings human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . 3000v machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c1010-d) . . . . . . . . . . 1000v latch-up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 44 ld qfn package ( notes 6 , 7 ) . . . . . . . . 25 1.5 junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions input supply voltage range, vdd . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v output voltage range, vout. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54v to 5.5v operating junction temperature range, t j . . . . . . . . . . . .-40c to +125c ambient temperature range, t a . . . . . . . . . . . . . . . . . . . . . -40c to +85c 5v (vr5) supply total supplied current ( note 8 ) . . . . . . . . . . . . . . . . . 5ma 5v ldo supply (vdrv) ( note 5 ) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 80ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. output current is limited by device thermal dissipation. 6. ? ja is measured in free air with the componen t mounted on a high-effective thermal conductivity test board with ?direct attach? fe atures. see tb379 . 7. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. total of current used by pull-ups to sda, scl, salr t, ddc, en, and pg (including push-pull configuration). electrical specifications v dd = 12v. typical values are at t a = +25c. boldface limits apply across the operating ambient temperature range, t a -40c to +85c parameter test conditions min ( note 14 )typ max ( note 14 )unit ic input and bias supply characteristics idd supply current f sw = 200khz - 26 50 ma f sw = 1.33mhz - 50 80 ma idd device disabled current e n = 0v, smbus inactive, vdd = ? 12v, f sw ? = ? 1.33mhz - 20 40 ma vr5 reference output voltage vdd > 6v, i < 5ma 4.5 5.0 5.5 v v25 reference output voltage for reference only, vr > 3v 2.25 2.5 2.75 v vr6 reference output voltage for reference only, vdd = 12v 5.5 6.1 6.6 v vdrv 5v output voltage ( note 9 )v dd > 6.0v; 0 to 80ma 4.5 5.25 5.5 v output characteristics output voltage adjustment range v in > v out + 1.1v 0.54 - 5.5 v output voltage set-point accuracy ( note 11 ) across line, load, temperature variation 0.72 < v out <5.50 -1 - 1 % v out output voltage set-point resolution ( note 10 ) set using pmbus command - 0.025 - % v out output voltage positive sensing bias cu rrent vsen[0,1] p = 4v (negative = sinking) -100 20 100 a output voltage negative sensing bias current vsen[0,1] n = 0v - 20 - a logic input/output characteristics logic input leakage current logic i/o - multimode pins -100 - 100 na logic input low, v il -- 0.8 v logic input high, v ih 2 --v logic output low, v ol 2ma sinking - - 0.5 v logic output high, v oh 2ma sourcing 2.25 --v
zl8802 fn8760 rev.3.00 page 9 of 91 nov 8, 2017 pwm output characteristics pwm output low 2ma sinking - - 0.5 v pwm output high 2ma sourcing 4.25 --v pwm tri-state input bias current (pwmh0, 1) v pwm = 2.5v - - 10 a pwm tri-state transition (always starts from low) 10pf maximum load 1 s oscillator and switching characteristics switching frequency range 200 - 1334 khz switching frequency set-point accuracy -5 - 5 % minimum sync pulse width 50% to 50% 150 --ns input clock frequency drift tolerance maximum allowed drift of external clock -10 - 10 % pmbus clock frequency ( note 12 ) 100 - 400 khz power management soft start/ramp characteristics ton-delay/toff-delay range set using pmbus command 0 5000 ms ton-delay accuracy 2-phase ton-delay > 4ms - +/-1 - ms toff-delay accuracy set to immediate off -0/+1 ms ton-rise/toff-fall duration range set using pmbus command (2-phase or 2-channel only) 0.0 100 ms ton-rise/toff-fall duration accuracy 2-phase or 2-channel only - 250 - s monitoring and fault management input voltage monitor and fault detection vdd/vin uvlo threshold range 2.85 - 16 v vdd/vin monitor accuracy full scale (fs) = 14v - 2 - % fs vdd/vin monitor resolution full scale (fs) = 14v - 0.15 - % fs vin uv fault response delay - 100 - s input current input current sense differential input voltage v iinp -v iinn 0 - 20 mv input current sense input offset voltage v iinp -v iinn -100- v input current sense accuracy % of full scale (20mv) - 5 - % fs output voltage monitor and fault detection vout monitor accuracy fs = v set voltage (vout) -2 - 2 % fs vout monitor resolution fs = v set voltage (vout) - 0.15 - % fs vout uv fault response delay -10- s output current output current sense resolution low range 25mv full scale - 37.5 - v medium range 35mv full scale - 56.25 - v high range 50mv full scale - 75.0 - v output current sense input bias current vout referenced isena0 or isena1 -100 - 100 na isenb0 or isenb1 -25 - 25 a output current sense monitor and fault detection output current dcr monitor temperature compensation configurable through pmbus 0 12700 ppm/c electrical specifications v dd = 12v. typical values are at t a = +25c. boldface limits apply across the operating ambient temperature range, t a -40c to +85c (continued) parameter test conditions min ( note 14 )typ max ( note 14 )unit
zl8802 fn8760 rev.3.00 page 10 of 91 nov 8, 2017 tmon bias monitor and fault detection tmon uvlo threshold range using tmon pin with 16:1 resistor divider 2.85 ? 5 v tmon accuracy ( note 13 ) full scale (fs) = 1.15v -2 ? 2 % fs tmon resolution full scale (fs) = 1.15v ? 0.15 ? % fs tmon uv/ov fault response delay ? 200 ? s temperature sensing internal temperature sensor internal temperature accuracy tested at +100c -5 ? 5 c internal temperature resolution ?1?c thermal protection threshold (junction temperature) factory default ? 125 ? c configurable through pmbus -40 ? 125 c external temperature sensor: xtemp0 and xtemp1 external temperature accuracy filter capacitance <100pf - 5 - c external temperature resolution ?1?c thermal protection threshold factory default ? 125 ? c configurable through pmbus -40 ? 125 c notes: 9. output current is limited by device thermal dissipation. 10. percentage of full scale (fs) with temperature compensation applied. 11. v out measured at the termination of th e vsenxp and vsenxn sense points. 12. for operation at 400khz, see pmbus power system management prot ocol specification part 1, section 5.2.6.2 for timing paramet er limits. 13. does not include errors due to resistor divider tolerances. 14. compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. electrical specifications v dd = 12v. typical values are at t a = +25c. boldface limits apply across the operating ambient temperature range, t a -40c to +85c (continued) parameter test conditions min ( note 14 )typ max ( note 14 )unit
zl8802 fn8760 rev.3.00 page 11 of 91 nov 8, 2017 zl8802 overview digital-dc architecture overview the zl8802 is an innovative mixe d-signal power conversion and power management ic based on intersil?s patented digital-dc technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. the zl8802 dc/dc controller is a dual channel, dual phase controller based on an architectu re that does not require loop compensation. the zl8802?s full digital loop achieves precise control of the entire power conversion proce ss with no software required resulting in a very flexible device that is also very easy to use. the chargemode control algorithm is implemented to respond to output current changes within a single pwm switching cycle. this achieves a smaller total output vo ltage variation with less output capacitance than traditional pwm controllers. an extensive set of power management functions are fully integrated and can be configured using simple pin conn ections. the user configuration can be saved in an internal nonvolatile memory (nvram). additionally, all functions can be configured and monitored through the smbus hardware interface using standard pmbus commands, allowing ultimate flexibility. the zl8802 is compliant with the pmbus power system management protocol specification part i and ii version 1.2. when enabled, the zl8802 is im mediately ready to regulate power and perform power management tasks with no programming required. advanced configuration options and real-time configuration change s are available through pmbus commands if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. integrated subreg ulation circuitry enables single supply operation from any supply between 4.5v and 14v with no bias supplies needed. the zl8802 can be configured by simply connecting its pins according to the tables provid ed in the following sections. additionally, a comprehe nsive set of online tools and application notes are available to help simp lify the design process. an evaluation board is also availa ble to help the user become familiar with the device. this board can be evaluated as a standalone platform using pin configuration settings. powernavigator?, a windows base d gui, is also provided to enable full configuration and monitoring capability through the pmbus interface and the included usb cable. power management overview the zl8802 incorporates a wide range of configurable power management features that are simple to implement with no external components. additiona lly, the zl8802 includes circuit protection features that contin uously safeguard the device and load from damage due to unexpected system faults. the zl8802 can continuously monitor input voltage and current, output voltage and current, internal te mperature, and the temperature of two external thermal diodes. a power-good output signal is also included to enable power- on reset functionality for an external processor. all power management functions ca n be configured using either pin configuration techniques de scribed in this document or through the smbus interface using pmbus commands. monitoring parameters can also be preconfigured to provide alerts for specific conditions. the ? pmbus command summary ? on page 22 contains a listing of all the pmbus commands supported by the zl8802 and a deta iled description of the use of each of these commands. pin-strap pins to simplify circuit design, the zl8802 incorporates patented pin-strap pins that allow the user to easily configure many aspects of the device with no programming. most power management features can be configured using these pins. the pin-strap pins will read the value of the resistor connected to those pins when power is applied to the device and set certain device configuration settings as specified by those resistor values. device configuration settings are made when connecting a finite value resistor (in a specified rang e) between the pin-strap pin and sgnd. standard 1% resistor va lues are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. smbus: almost any zl8802 function can be configured through the smbus interface using standard pmbus commands. additionally, any value that has been configured using the pin-strap setting method can also be reconfigured and/or verified through smbus. ? pmbus command detail ? on page 27 explains the use of the pmbus commands in detail. table 2. pin tied to value low (logic low) <0.8 vdc open (n/c) no connection high (logic high) >2.0 vdc resistor to sgnd set by resistor value multimode pin pin-strap settings resistor settings multimode pin logic high open logic low v25 figure 3. pin-strap and resistor settings
zl8802 fn8760 rev.3.00 page 12 of 91 nov 8, 2017 configurable pins numerous operating parameters can be set using the pin-strap resistor setting method: smbus address (pin 5, sa), output voltage (pins 10 and 11, vset0, 1), switching frequency (pin 44, sync), input voltage undervoltage lockout (pin 13, uvlo). ascr gain is set by ascrcfg (pin 8). cfg (pin 9) sets the power stage settings such as over and undercurrent limits. the smbus device address is the only parameter that must be set by a pin-strap setting pin. all other device parameters can be set through pmbus. the device ad dress is set using the sa pin. smbus device address selection (sa) when communicating with multiple smbus devices using the smbus interface, each device mu st have its own unique address so the host can distinguish be tween the devices. the device address can be set according to the pin-strap options listed in table 3 . when operating in 2-channel mode, care must be taken when using sequential pmbus addresses. because ddc addresses are automatically set us ing the pmbus address, it is possible for a device with a p mbus address immediately after a 2-channel zl8802 to be automatica lly configured with the same ddc address as one of the zl8802 channels, which could cause unintended operating modes. for th is reason, do not use the next higher pmbus address when using the zl8802 as a 2-channel device. see pmbus command ? ddc_config (d3h) ? on page 65 for details. the smbus address cannot be changed with a pmbus command. output voltage and vout_max selection (vset0, 1) the output voltage can be set to any voltage between 0.54v and 5.5v provided that the input volt age is higher th an the desired output voltage by at least 1.1v. using the pin-strap method, v out can be set to any of the voltages shown in table 4 . v out can also be set using a pmbus command. vout_max is also determined by this pin-strap setting, and is 15% greater than the vset0 and vset1 voltage settings by default, however, vout_max can be changed through pmbus. switching frequency setting (sync) the device?s switching frequency is set from 200khz to 1333khz using the pin-strap method as shown in table 5 , or by using a pmbus command. the zl8802 gene rates the device switching frequency by dividing an internal precision 16mhz clock by integers from 11 to 80.500khz (n = 32) and 1000khz (n = 16) are not recommended operating frequencies; use 533khz and 1067khz for best performance. table 3. smbus device address selection rsa (k ? ) smbus address rsa (k ? ) smbus address low 40h 42.2 51h open 42h 46.4 52h 10 41h 51.1 53h 11 43h 56.2 54h 12.1 44h 61.9 55h 13.3 45h 68.1 56h 14.7 46h 75 57h 16.2 47h 82.5 58h 17.8 48h 90.9 59h 19.6 49h 100 5ah 21.5 4ah 110 5bh 23.7 61h 121 5ch 26.1 4ch 133 5dh 28.7 4dh 147 5eh 31.6 4eh 162 5fh 34.8 4fh 178 60h 38.3 50h table 4. output voltage settings rvset (k ? ) vout (v) rvset (k ? )vout (v) low 1.00 38.3 1.30 open 1.20 42.2 1.40 high 0.90 46.4 1.50 10 0.60 51.1 1.60 11 0.65 56.2 1.70 12.1 0.70 61.9 1.80 13.3 0.75 68.1 1.90 14.7 0.80 75 2.00 16.2 0.85 82.5 2.10 17.8 0.90 90.9 2.20 19.6 0.95 100 2.30 21.5 1.00 110 2.50 23.7 1.05 121 2.80 26.1 1.10 133 3.00 28.7 1.15 147 3.30 31.6 1.20 162 4.00 34.8 1.25 178 5.00 table 5. switching frequency settings rsync (k ? ) freq (khz) rsync (k ? )freq (khz) low 302 23.7 457 open 400 26.1 533 high 485 28.7 571 10 200 31.6 615 11 222 34.8 727 12.1 242 38.3 800
zl8802 fn8760 rev.3.00 page 13 of 91 nov 8, 2017 the zl8802 incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other intersil digital power devices. by default, the sync pin is configured as an input. the device will automatically check for a clock sign al on the sync pin each time en is asserted. the zl8802?s oscillator will then synchronize with the rising edge of the external clock. the incoming clock signal must be in the range of 200khz to 1.33mhz and must be stable when the enable pin (en0, en1) is asserted. when using an external clock, the frequencies are not limited to discrete values as when using the internal clock. the external clock signal must not vary more than 10% from its initial value and should have a minimum pulse width of 150ns. in the event of a loss of the external clock signal, the output voltage may show transient overshoot or undershoot. if loss of synchronization occurs, the zl8802 will automatically switch to its internal oscillato r and switch at its programmed frequency. when used in a multiphase (4-, 6-, and 8-phase) application, the sync pin of one of the devices mu st be configured as an output. the device will run from its internal oscillator and will drive the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. the switching frequency can be set to any value between 200khz and 1.33mhz using a pmbus command. the available frequencies below 1.33mhz are defined by f sw = 16mhz/n, where 12 n 80. if a value other than f sw = 16mhz/n is entered using a pmbus command, the internal circuitry will select the switching frequency value using n as a whole number to achieve a value close to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 20). input voltage undervoltage lockout setting (uvlo) the input undervoltage lockout (uvlo) prevents the zl8802 from operating when the input falls belo w a preset threshold, indicating the input supply is out of its sp ecified range. the input voltage undervoltage lockout threshold can be set between 4.18v and 16v using the pin-strap me thod as shown in table 6 . uvlo can also be set or changed using the vin_uv_fault_limit command. when an input undervoltage fault condition occurs, the user can determine the desired response to the fault condition. the following input undervoltage pr otection response options are available: ? shut down and stay off until the fault has cleared and the device has been disabled and reenabled. ? shut down and restart continuously after a delay. refer to ? pmbus command detail ? on page 27 for details on how to select specific overvoltage fault response options using the vin_uv_fault_response command. when controlling the zl8802 exclusively through the pmbus, a high voltage setting for uvlo can be used to prevent the zl8802 from being enabled until a lower voltage for uvlo is set using the vin_uv_fault_limit command. configuration setting (cfg) the configuration pin (cfg) sets several device configuration settings allowing the device to be used in applications without the need for loading configuration fi les. the settings are shown in table 7 . when using the zl8802 in a 4-phase application, the master device address must be 1 higher than the slave address. this must be done for the two devices to be recognized as part of a current sharing group. see pmbus command ? ddc_config (d3h) ? on page 65 for details. 13.3 267 42.2 842 14.7 286 46.4 889 16.2 320 51.1 1067 17.8 364 56.2 1143 19.6 381 61.9 1231 21.5 432 68.1 1333 table 5. switching frequency settings (continued) rsync (k ? ) freq (khz) rsync (k ? )freq (khz) table 6. input voltage undervoltage lockout setting ruvlo (k ? ) uvlo (v) ruvlo (k ? )uvlo (v) low 5.50 46.4 7.42 open 4.50 51.1 8.18 high 10.80 56.2 8.99 26.1 4.18 61.9 9.90 28.7 4.59 68.1 10.90 31.6 5.06 75 12.00 34.8 5.57 82.5 13.20 38.3 6.13 90.9 14.54 42.2 6.75 100 16.00 table 7. configuration settings rcfg (k ) page 0 page 1 circuit average oc limit (a) peak oc limit (a) average oc limit (a) peak oc limit (a) 10 25 28 25 28 2 output 11 35 37.5 35 37.5 2 output 12.1 45 48 45 48 2 output 13.3 55 60 55 60 2 output 14.7606560652 output 16.2 65 70 65 70 2 output 17.8 35 37.5 25 28 2 output 19.6454825282 output 21.5 55 60 25 28 2 output 23.7 45 48 35 37.5 2 output
zl8802 fn8760 rev.3.00 page 14 of 91 nov 8, 2017 chargemode control (ascr) setting (ascrcfg) the device?s chargemode response can be optimized by adjusting the ascr gain and residual settings, either by using the ascrcfg pin-strap resistor method as shown in table 8 , or by using the ascr_config pmbus command. when using table 8 , the ascr residual is fixed at 90. start-up and shutdown settings the device?s start-up and shutdown settings can be set by using the following pmbus commands: ton_delay: sets the time from a low to high en0 or en1 transition, or the receipt of an operation command through pmbus, to the start of an output voltage ramp. ton_rise: sets the time from the end of the ton_delay to the output voltage reaching regulation. toff_delay: sets the time from a high to low en0 or en1 transition, or the receipt of an operation command through pmbus, to the start of an output voltage ramp down. toff_fall: sets the time from the end of the toff_delay to the output voltage reaching 0v. note that in the case of 2-chan nel operation, these settings will apply to both channels. each channel can be configured to have different settings by using the ton_delay, ton_rise, toff_delay, and toff_fall pmbus commands. internal bias regulators and input supply connections the zl8802 employs internal low dropout (ldo) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. the internal bias regulators are as follows: vr6 : the vr6 ldo provides a regulated 6.1v bias supply for internal circuitry. it is powered from the vdd pin. a 4.7f ceramic x7r filter capacitor to sgnd is required at the vr6 pin. keep this net as small as possible and avoid routing this trace near any switching signals. vr5 : the vr5 ldo provides a regulated 5.1v bias supply for internal circuitry. it is powered from the vdd pin. a 4.7f ceramic x7r filter capacitor to sgnd is required at the vr5 pin. this supply can be used for to provide a pull-up supply as long as load current does not exceed 5ma. 26.155603537.52 output 28.7556045482 output 31.6 25 28 35 37.5 2 output 34.8252845482 output 38.3252855602 output 42.23537.545 482 output 46.43537.555 602 output 51.1 45 48 55 60 2 output 56.2252825282-phase 61.9 35 37.5 35 37.5 2-phase 68.1454845482-phase 75 55 60 55 60 2-phase 82.5657065702-phase 90.93537.53537.54-ph master 1003537.53537.54-ph slave 110454845484-ph master 121454845484-ph slave 133556055604-ph master 147556055604-ph slave 162657065704-ph master 178657065704-ph slave low 20 22.5 20 22.5 2-phase open 20 22.5 20 22.5 2 output high 35 37.5 35 37.5 2 output table 8. chargemode control (ascr) settings ascrcfg k ? ) gain p0 gain p1 ascrcfg (k ? ) gain p0 gain p1 10 200 200 51.1 800 600 11 200 400 56.2 800 800 12.1 200 600 61.9 800 1000 13.3 200 800 68.1 1000 200 14.7 200 1000 75 1000 400 table 7. configuration settings (continued) rcfg (k ) page 0 page 1 circuit average oc limit (a) peak oc limit (a) average oc limit (a) peak oc limit (a) 16.2 400 200 82.5 1000 600 17.8 400 400 90.9 1000 800 19.6 400 600 100 1000 1000 21.5 400 800 110 100 100 23.7 400 1000 121 300 300 26.1 600 200 133 500 500 28.7 600 400 147 700 700 31.6 600 600 162 900 900 34.8 600 800 178 1100 1100 38.3 600 1000 low 300 300 42.2 800 200 open 500 500 46.4 800 400 high 700 700 table 8. chargemode control (ascr) settings (continued) ascrcfg k ? ) gain p0 gain p1 ascrcfg (k ? ) gain p0 gain p1
zl8802 fn8760 rev.3.00 page 15 of 91 nov 8, 2017 v25 : the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node. a 4.7f ceramic x7r filter capacitor to sgnd is required at the v25 pin. this voltage should only be used to set pin-strap pins to the high state. vdrv : the vdrv ldo provides a regulated 5.25v bias supply for external mosfet driver ics or drmos integrated drivers/fets. a 4.7f ceramic x7r filter capacitor to pgnd is required, however, additional capacitance will be needed as specified by the mosfet driver or drmos device selected. the maximum rated output current is 80ma, but device thermal limits must be considered. the power dissipated by the vdrv supply will be (vin-5.25v) x idrv, where idrv is the current supplied by the vdrv bias supply. vdrv is en abled by leaving the vdrven unconnected (floating) or connecting it to vr5, and is disabled by connecting vdrven to ground. note: the internal bias regulators, vr6, vr5, and v25, are not designed to be outputs for powering other circuitry. the multimode pins can be connected to the v25 pin for logic high settings, and the vr5 supply can be used to provide up to 5ma of pull-up current for the sda, scl, salrt, ddc, and pg pins. operation with 5v vdd: when operating the zl8802 at voltages below 5.5v, the vr6 and vr5 supplies should be connected directly to vdd for best performance. the vdrv supply should not be used; the 5v vdd supply should be used instead for powering drmos and mosfet driver ics. start-up procedure the zl8802 follows a specific internal start-up procedure after power is applied to the vdd pin, as shown in figure 5 . the device requires approximately 60ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. when this process is completed, the device is ready to accept commands through the serial interface and the device is ready to be enabled. if the device is to be synchronized to an external clock source, the clock freque ncy must be stable before asserting the en pin. when enabled, the device requires approximately 2ms before its output voltage will be allowed to start its ramp-up process. after the ton-delay period has expired, the output will begin to ramp towards its target voltage according to the preconfigured ton-rise time. v in should be above the zl8802?s uvlo limit (vin_uv_fault_limit) before the enable pin is driven high. following this sequence will result in the most consistent turn-on delays. if a configuration file is needed to ensure proper circuit operation , when v in is first applied to the zl8802, for example, during initial pcb turn-on and test, the enable pin must be held low by some means until the zl8802 configuration file can be loaded. if the enable pin is no t held low, then the zl8802 may attempt to turn on with incorrect configuration settings, possibly causing circuit failure. in those cases in which a configuration file is needed to ensure proper circuit operation and the enable pin cannot be held low during the initial application of power, two options are available: ? limit v in to 3.0v during initial testing. the zl8802 configuration file can be loaded when v in is as low as 3.0v. when the configuration file is loaded v in can be increased to the normal input voltage range. ?use a 100k pin-strap resistor to set uvlo to 16v. this will keep the zl8802 disabled while the configuration file is loaded. ensure that the vin_uv _fault_limit command is the last command in the configuration file. ton-delay and rise times ton- and toff-delay and ramp times are initially set to 5ms. in some applications, it may be nece ssary to set a delay from when an enable signal is received un til the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features can be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the zl8802 gives the system designer several options for precisely and independently controlling both th e delay and ramp time periods. the ton-delay time begins when the en pin is asserted. the ton-delay time is set using the pmbus command ton_delay. the ton-rise time enables a precisely controlled ramp to the nominal v out value that begins when the ton-delay time has v in vdd vr6 vr5 v in vdd vr6 vr5 4.5v < v in < 5.5v 5.5v < v in < 14v figure 4. vr supply connections figure 5. zl8802 internal start-up procedure input power applied internal memory check 50ms C 70ms device will ignore an enable signal or pmbus commands device ready pre-ramp delay minimum 2ms delay between enable signal and start of output ramp. additional delay may be added with pmbus command
zl8802 fn8760 rev.3.00 page 16 of 91 nov 8, 2017 expired. the ramp-up is monotonic and its slope can be precisely set using the pmbus command ton_rise. the ton-delay and ton-ramp times can be set using pmbus commands ton_delay and ton_rise over the serial bus interface. when the ton-delay time is set to 0ms, the device will begin its ramp after the internal circuitry has initialized the ton-delay and ton-ramp times can be set using pmbus commands ton_delay and ton_rise over the serial bus interface. when the ton-delay time is set to 0ms, the device will begin its ramp after the internal circuitry has initialized which takes approximately 2ms to complete. the ton-rise time can be set to values less than 2ms; however, the ton-rise time should be set to a value greater than 500s to prev ent inadvertent fault conditions due to excessive inrush current. a lower ton-rise time limit can be estimated using the formula: ton-rise = c out *v out /i limit where c out is the total output capacitance, v out is the output voltage, and i limit is the current limit setting for the zl8802. when using interdevice current sharing (4 phases), the output voltage rise time varies by app lication. the rise time can be adjusted using the pmbus command multi_phase_ramp_gain. higher gain values produce faster turn-on ramps. typical multi_phase_ramp_gain values range between 1 and 10; the default value is 3. the slew rate of the output voltage during ramp-up is directly proportional to this gain, as well as the input voltage (v in ) and the device switching frequency (frequency_switch). use the following formula to calculate the slew rate of the output voltage during turn-on: slew rate (mv/ms) = 14*(vin)*(multi_phase_ramp_gain) * (frequency_switch in mhz) the resulting total rise time can then be calculated: rise time = output voltage/slew rate enable pin operation and timing the enable pins (en0 and en1) are used to enable and disable each channel of the zl8802. when operated as a 2-phase converter, use en0 and ground en1. the enable pins should be held low whenever a configuration file or script is used to configure the zl8802, or a pmbus command is sent that could potentially damage the applicatio n circuit. when the zl8802 is used in a self-enabled mode, for example, when en0 or en1 is tied to vr5, or to a resistor divider to vin, the user must consider the zl8802's default factory setting s. when a configuration file is used to configure the zl8802, the factory default settings are restored to both the user and default stores to set the zl8802 to an initialized state. because the default state of the zl8802 is to be enabled when the enable pin is high, it is possible for the zl8802 to be enabled while the pmbus commands are sent to the zl8802 during the configuration process. the enable pin is edge triggered to achieve fast turn-off times. as a result, minimum enable high an d enable low pulse widths must be observed to ensure correct operation. the minimum high and low pulse widths are dependent on the configured rise, fall, and delay times and can be calculated using equations 1 and 2 : en low and en high times shorter than these minimums may result in the device not respondi ng to the trailing edge of the pulse. for example, a en low pulse below the en low minimum pulse width may stay in the off state until a valid en low pulse is applied to the en pin. when operating the ic in 2 channel mode, avoid transitioning en0 or en1 high within 1ms of the beginning of the opposite channel?s start-up ramp. for ex ample, if the page 0 output (vsen0, pwm) begins to ramp up at the end of the ton_delay of 5ms, en1 should not transition high between 4ms and 6ms. power-good the zl8802 provides a power-good (pg0, pg1) signal for each channel that indicates the output voltage is within a specified tolerance of its target level an d no fault condition exists. by default, the pg pin will assert if the output is within 10% of the target voltage. these limits and the polarity of the pin can be changed using pmbus commands. a pg delay period is defined as the time from when all conditions within the zl8802 for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the zl8802 pg delay is set equal to 1ms. the pg delay can be set using a pmbus command as described in ? power_good_delay (d4h) ? on page 66 . power management functional description output overvoltage protection the zl8802 offers an internal output overvoltage protection circuit that can be used to prot ect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a programmable threshold set to 10% higher than the target output voltage (the default setting). if the vsen voltage exceeds th is threshold, the pg pin will deassert and the device can then respond in the following ways: ? shut down and stay off until the fault has cleared and the device has been disabled and reenabled. ? shut down, and when the fault is no longer present, attempt to restart. refer to ? vout_ov_fault_response (41h) ? on page 37 for details on how to select specif ic overvoltage fault response options using the vout_ov_fault_response command. output prebias protection the zl8802 provides prebiased start-up operation in 2-channel and single device 2-phase operat ion. prebias protection is not provided when operating in current sharing 4-, 6- or 8-phase configurations. an output preb ias condition exists when an externally applied voltage is present on a power supply's output before the power supply's control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a prebias condition exists at the output. the zl8802 provides prebias protection by sampling the output voltage before initiating an output ramp. (eq. 1) en low toff_delay toff_fall 10.5ms ++ ? en high ton_delay ton_rise power_good_delay 5.5ms ++ + ?
zl8802 fn8760 rev.3.00 page 17 of 91 nov 8, 2017 if a prebias voltage lower than the desired output voltage is present after the ton-delay time the zl8802 starts switching with a duty cycle that matches the prebias voltage. this ensures that the ramp-up from the preb ias voltage is monotonic. the output voltage is then ramped to the desired output voltage at the ramp rate set by the ton_rise command. the resulting output voltage rise time will vary depending on the prebias voltage, but the total ti me elapsed from the end of the ton-delay time to when the ton-rise time is complete and the output is at the desired value will match the preconfigured ramp time (see figure 6 ). if a prebias voltage higher than the target voltage exists after the preconfigured ton-delay time and ton-rise time have completed, the zl8802 starts switching with a duty cycle that matches the prebias voltage. this ensures that the ramp-down from the prebias voltage is monotonic. the output voltage is then ramped down to the desired output voltage if a prebias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will stay off. output overcurrent protection the zl8802 can protect the power supply from damage from an overloaded or shorted output. wh en the current limit threshold has been selected (see ? current limit configuration ? on page 18 ), the user can determine the desired response to the fault condition. the following overcurrent protection response options are available: ? shut down and stay off until the device has been disabled and reenabled. ? shut down and restart continuously after a delay. refer to the ? pmbus command detail ? on page 27 for details on how to select specific overvolt age fault response options using the iout_oc_fault_ response command. sps current sensing by default, the zl8802 senses current by utilizing the imon output from the isl9922x smart power stage (sps). a 6:1 resistor divider is needed between the sps imon output and the isena and isenb inputs of the zl8802, as shown in figure 7 . using an isl9922x device will provide the best current sense accuracy with no action needed from the user. drmos current sensing if a drmos device must be used, the zl8802 can also use the inductor dcr current sensing te chnique. current sensing is achieved with an r/c network as shown in figure 8 . for the voltage across c 1 to reflect the voltage across the dcr of the inductor, the time constant of the inductor must match the time constant of the rc network. this capacitor, shown as c 1 in figure 8 , should be an x7r or better dielectric, and c 1 should be placed as close to the zl8802 as possible for the best noise performance. the l and dcr values should be set using the indu ctor and iout(0/1)_cal_gain figure 6. output responses to prebias voltages ton delay ton rise desired output voltage prebias voltage v out time ton delay ton rise desired output voltage prebias voltage v out time v prebias < v target v prebias > v target figure 7. sps current sensing v out zl8802 pwmh vdrv isena isenb vdd v in 6 * r isl99227b r pwm imon refin vin vin sps sw v out zl8802 pwmh vin isena isenb v in r 1 c 1 l drmos dcr l c r dcr l rc ? ? ? 1 1 / ? ? (eq. 3)
zl8802 fn8760 rev.3.00 page 18 of 91 nov 8, 2017 commands. for l , use the average of the nominal value and the minimum value. include the effects of tolerance, dc bias, and switching frequency on the indu ctance when determining the minimum value of l . use the typical room temperature value for dcr . current limit configuration the zl8802 gives the power supply designer several choices for the fault response during overcurr ent or undercurrent conditions. the user can select the number of violations allowed before declaring fault, a blanking time , and the action taken when a fault is detected. these parameters can be configured using the isense_config command. the blanking time represents the time when no current measurement is taken. this is to avoid taking a reading just after a current load step (less accurate due to potential ringing). it is a configurable parameter from 0 to 832ns. zl8802 provides an adjustable maximum full scale sensing range. three ranges are ava ilable: 25mv, 35mv, and 50mv maximum input voltage. by default, current sensing is enabled during the inductor current down-slope period of the switchin g period (d?). in applications where the steady state duty cycle is >0.5, for example, a 5v to 3.3v converter, the zl8802 can be configured to sense current during the inductor up-slope peri od of the switching cycle (d). the user has the option of selecting how many consecutive overcurrent readings must occur before an overcurrent fault and subsequent shutdown are initiated. ei ther 1, 3, 5, 7, 9, 11, or 13 consecutive faults can be selected. the current limit thresholds are set with four commands: 1. iout_oc_fault_limit ? this sets the overcurrent threshold that must be exceeded by the number of consecutive times chosen in isense_config. 2. iout_uc_fault_limit ? this is the same as iout_oc_fault_limit, but represents the negative current that flows lower fet during the d? interval. large negative currents can flow during faults such as a higher voltage rail being shorted to a lower voltage rail. 3. iout_avg_oc_fault_limit ? this limit is similar to iout_oc_fault_limit, but the limit represents an average reading over several switching cycles. because it is an average, the response time is slower, but the limit can be set closer to the maximum average expected output current. 4. iout_avg_uc_fault_limit ? this limit is similar to iout_avg_oc_fault_limit, but represents the negative current that flows lower fet during the d? interval. input current monitor the input current can be monitored through the iinn and iinp pins. the input current monitor input should be connected across a current sensing resistor in seri es with the input supply. the iinp pin is connected to the input supply side of the current sense resistor and the iinn pin is connected to the zl8802 vdd side of the current sense resistor. using the iin_scale command, set the current sense resistor value. select the current sense resistor value such that the maximum expected input current times the current sense resistor value does not exceed the maximum current sensing input voltage of 20mv. if this feature is not used, iinn and iinp should be tied to vdd. thermal overload protection the zl8802 includes an on-chip th ermal sensor that continuously measures the internal temperature of the die. this thermal sensor is used to provide both over-t emperature and under-temperature protection. if the over-temperature limit is exceeded, or the temperature falls below the under-temperature limit, the zl8802 is shut down. the over-temperatu re and under-temperature limits are set by the ot_fault_limit and ut_fault_limit respectively. the zl8802 will not attempt to re start until the temperature has fallen below the ot_warn_limit fo r over-temperature faults or has risen above the ut_warn_limi t for under-temperature faults. the default temperature limits are +125c and -45c, but the user can set the limits to differen t values if desired. note that setting a higher over-temperature or under-temperature limit may result in permanent damage to the device. when the device has been disabled due to an internal temperature fault, the user can select one of several fault response options as follows: ? shut down and stay off until the fault has cleared and the device has been disabled and reenabled. ? shut down and restart continuously after a delay. refer to ? pmbus command detail ? on page 27 for details on how to select specific overvoltage fault response options using the ot_fault_response and ut_f ault_ response commands. voltage tracking numerous high performance sy stems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics, and other advanced processor devices that require multiple supply voltages to power a single die. in most ca ses, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to manufacturer specifications. the zl8802 integrates a tracking scheme that allows one of its outputs (channel 0 or channel 1), or the single output in a dual phase application, to track a voltage that is applied to the vtrk pin with no external components required. the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. coincident . this mode configures th e zl8802 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin until it reaches its desired output voltage. the device that is tracking another output voltage (s lave) must be set to its desired steady state output voltage, that is, the vout_command is set to the final output voltage. ratiometric . this mode configures the zl8802 to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string can be used to configure a different tracking ratio. the device that is tracking another ou tput voltage (slave) must be set to its desired steady-state output voltage, that is, the vout_command is set to the final output voltage.
zl8802 fn8760 rev.3.00 page 19 of 91 nov 8, 2017 the master zl8802 device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not conf igured for tracking mode. the maximum tracking rise time is 1v /ms. the slave device must be enabled before the master. any device that is configured for tracking mode will ignore its ton-delay and ton-rise settings and its output will take on the turn-on/turn-off characteristics of the reference voltage present at the vtrk pin. tracking mode can be configur ed by using the track_config command. note that current sharing groups th at are also configured to track another voltage do not offer prebias protection; a minimum load should therefore be enforced to avoid the output voltage from being held up by an outside force. external voltage monitoring the voltage monitoring (tmon) pin is available to monitor the voltage supply for the external driver ic. the tmon input must be scaled by a 16:1 ratio to read-b ack the tmon voltage correctly. a 100k and 6.65k resistor divider is recommended. overvoltage and undervoltage fault thresholds can be set using mfr_tmon_ov_fault_limit and mfr_ tmon_uv_fault_limit commands. the response to these limits are set using the tmon_ov_fault_response an d tmon_ uv_fault_response commands. to ignore the tmon input, set the tmon_ov and _uv_fault_response to 00h. when the device has been disabled due to tmon fault, the user can select one of several fault response options as follows: ? shut down and stay off until the fault has cleared and the device has been disabled and reenabled. ? shut down and restart continuously after a delay. smbus communications the zl8802 provides a smbus digital interface. the zl8802 can be used with any stan dard 2-wire smbus host device. in addition, the device is compatible with s mbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. pull-up resistors are required on the smbus. the pull-up resistor can be tied to vr5 or to an external 3.3v or 5v supply as long as this voltage is present before or during device power-up. the ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. the minimum pull-up resistance should be limited to a value that enables any device to assert the bu s to a voltage that will ensure a logic 0 (typically 0.8v at the de vice monitoring point) given the pull-up voltage (5v if tied to vr5) and the pull-down current capability of the zl8802 (nomina lly 4ma). a pull-up resistor of 10k is a good value for most applications. smbus data and clock lines shou ld be routed with a closely coupled return or ground plane to minimize coupled interference (noise). excessive noise on the data and clock lines that cause the voltage on these lines to cross the high and low logic thresholds of 2.0v and 0.8v respectively will cause command transmissions to be interrupted an d result in slow bus operation or missed commands. a 10k resistor on each line provides good performance on an smbus with fewer than 10 devices. the zl8802 accepts most standard pmbus commands. when enabling the device with on_off_config command, it is recommended that the enable pin is tied to sgnd. in addition to bus noise considerat ions, it is important to ensure that user connections to the smbus are compliant to the pmbus command standards. any device that can malfunction in a way that permanently shorts smbus lines will disable pmbus communications. incomplete pmbus commands can also cause the zl8802 to halt pmbus communications. this can be corrected by disabling, then reenabling the device. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between intersil digital-dc devices, and within the zl8802 itself. this dedicated bu s provides the communication channel between devices for featur es such as sequencing, fault spreading and current sharing. the ddc pin must be pulled-up to an external 2.5v to 5.0v supply , (or configured as a push-pull output using the user_global_config command) even if the zl8802 is operating stand-alone . in addition, the ddc pin must be pulled up or configured as a push-pull output before the enable pin is set high. push-pull mode can only be used when the zl8802 is operating stand-alone. the ddc pin on all digital-dc devices that utilize sequencing, fa ult spreading or current sharing must be connected together. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus to guarantee the rise time as follows: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor can be tied to vr5 or to an external 3.3v or 5v supply as long as this voltage is present before or during device power-up. generally, each device figure 9. tracking modes vo2 v out time coincident ratiometric vo1 vo2 v out time vo1 riset time r pu c load 1 ? s ? ? =
zl8802 fn8760 rev.3.00 page 20 of 91 nov 8, 2017 connected to the ddc bus presents approximately 12pf of capacitive loading. the ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. in power module applications, the user should consider whether to place the pull-up resistor on the module or on the pcb of the end application. the minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8v at the device monitoring point) given the pull-up voltage (5v if tied to vr5) and the pull-down current capability of the zl8802 (nominally 4ma). as with smbus data and clock lines, the ddc data line should be routed with a closely coupled retu rn or ground plane to minimize coupled interference (noise). ex cessive noise on the ddc signal can cause the voltage on this line to cross the high and low logic thresholds of 2.0v and 0.8v respectively and will cause command transmissions to be inte rrupted and result in slow bus operation or missed commands. fo r less than 10 devices on the ddc bus a 10k resistor provides good performance. phase spreading when multiple point-of-load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices have coincident rising edges. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements. because the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to i rms 2 are reduced. to enable phase spreading, all converters must be synchronized to the same switching clock. configuring the sync pin is described in ? configurable pins ? on page 12 . selecting the phase offset for the device is accomplished by selecting a device address according to equation 5 : the phase offset of each device can also be set to any value between 0 and 360 in 22.5 increments using the interleave pmbus command. output sequencing a group of intersil digital power devices can be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage before another supply reaching its operating voltage to avoid latch-up from occurring. multidevice sequencing can be achieved by configuring each device using the sequence pmbus command. multiple device sequencing is achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. the enable (en) pins of all device s in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven low to initiate a sequenced turn-off of the group. to achieve sequenced turn-off of a group of sequenced devices, all the devices should be configured to turn off using the ?soft-off?, or ramped down behavior, in the on_off_config pmbus command. when sequencing on, the first device to ramp up, called the ?prequel?, sends a message thro ugh the ddc bus to the next device, called the ?sequel? when the prequel?s power-good (pg) signal is driven high. when sequencing off, the sequel will send a message to the prequel to begin the prequel?s ramp down after the sequel has completed its own ramp down. sequencing can also be accomplished by connecting the enable pin of a sequel device to the po wer-good pin of a prequel device. sequencing is also achieved by using the ton_delay and ton_rise commands and choosing appropriate delay and rise durations such that sequel devices start after their associated prequel devices. the drawback to this method is that if a prequel device fails to start properly, its sequel device will still start and ramp on according to its delay and rise time settings. fault spreading digital-dc devices can be config ured to broadcast a fault event over the ddc bus to the other devices in the group. when a fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the ddc bus will shut down together if configured to do so, and will atte mpt to restart in their prescribed order if configured to do so. active current sharing the pwm outputs of the zl8802 are used in parallel to create a dual phase power rail. the device outputs will share the current equally within a few percent, assuming all external sensing element variations and tolerances are negligible. current sensing element tolerances must be taken into account, or adjusted for using the iout_cal_gain and io ut_cal_offset commands in any application. the zl8802 will current share between phases without utilizing output voltage droop. droop resistance is used in 4-phase current sharing to add artificial resistance in the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and pcb layout. (eq. 5) phase offset device address 45 ? ? = -r -r v reference v member i member i reference i out v out figure 10. active current sharing
zl8802 fn8760 rev.3.00 page 21 of 91 nov 8, 2017 when current sharing up to 2 zl8802s (4 phases total), the zl8802 uses a low-bandwidth, first-order digital current sharing technique to balance the unequal device output loading by aligning the load lines of member devices to a reference device. upon system start-up, the lowest numbered phase is defined as the reference phase and all othe r phases are member phases. the reference phase broadcasts its current over the ddc bus. the member phases use the referenc e current information to trim their reference voltages (v member ) to balance the current loading of each device in the system. figure 10 on page 20 shows that, for load lines with identical slopes, the member reference voltage is increased towards the reference voltage which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by the following equation 6 : where r is the value of the droop resistance. the vout_droop command is used to set the device output voltage droop to achieve 4-, 6- or 8-phase current sharing. 4-, 6-, and 8-phase current sharing groups must have their ddc and sync pins tied together to achieve current sensing and ensure accurate phase offsets between current sharing phases. temperature monitoring using xtemp pin each channel of the zl8802 supports measurement of an external device temperature using either a thermal diode integrated in a processor, fpga or asic, or us ing a discrete diode-connected 2n3904 npn transistor. figure 11 illustrates the typical connections required. a noise filtering capacitor, not exceeding 100pf, should be connected ac ross the external temperature sensing device. the external temperature sensors can be used to provide the temperature reading for over-temperature and under-temperature faults. the external sensors can also be used to provide more accurate temperature compensation for inductor dcr current sensing by being placed close to the inductor. these options for the external temperature sensors are selected using the user_config pmbus command. nonvolatile memory and security features the zl8802 has internal nonvolatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the device to a level that has been made available to them. during the initialization process, the zl8802 checks for stored values contained in its internal nonvolatile memory. the zl8802 offers two internal memory storage units that are accessible by the user as follows: user store : the user store is the most commonly used store. it provides the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer would use the user store to achieve this goal. default store : the default store is less commonly used. it provides a means to protect the circuit from damage by preventing the user from modi fying certain values that are related to the physical construction of the circuit. in this case, the original equipment manufacturer (oem) would use the default store in a protected mode and allow the user to restore the device to its default settings. in this case the user store would be available to the end-user for making changes, but would restrict the user from restoring the devi ce to the factory settings or modifying the default store. the user store takes priority over the default store. if there are no values set in the user or default store, then the device will use the pin-strap setting value. for details regarding protection of the user and default stores, see the password pmbus command. monitoring through smbus a system controller can monitor a wide variety of different zl8802 parameters through the smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be asserted when any number of preconfigured fault conditions occur. the device can also be monitored continuously for any number of power conversion parameters including, but not limited to, the following: ?input voltage ?output voltage ? input current ?output current ? internal junction temperature ? temperature of an external device ? switching frequency ? duty cycle ? fault status information the pmbus host should resp ond to salrt as follows: 1. zl device pulls salrt low. 2. pmbus host detects that salrt is now low, and performs transmission with alert respon se address to find which zl device is pulling salrt low. ?? member reference out member i i r v v ? ? ? ? figure 11. external temperature monitoring zl8802 xtempxp xtempxn zl8802 xtempxp xtempxn asic 100pf 100pf 2n3904 discrete npn embedded thermal diode
zl8802 fn8760 rev.3.00 page 22 of 91 nov 8, 2017 3. pmbus host talks to the zl devi ce that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. refer to ? pmbus command detail ? on page 27 for details on how to monitor specific parameters through the smbus interface. pmbus command summary code command name description type data format default value default setting 00h page selects controller 0, 1, or both r/w bit 00h page 0 controller addressed 01h operation enable/disable, margin settings r/w bit 00h immediate off, nominal margin 02h on_off_config on/off configuration settings r/w bit 17h enable pin control, active high 03h clear_faults clears faults write n/a n/a n/a 11h store_default_all stores values to default store write n/a n/a n/a 12h restore_default_all restores values from default store write n/a n/a n/a 15h store_user_all stores values to user store write n/a n/a n/a 16h restore_user_all restores values from user store write n/a n/a n/a 20h vout_mode reports v out mode and exponent read bit 13h linear mode, exponent = -13 21h vout_command sets nominal v out set-point r/w l16u n/a pin-strap setting 22h vout_trim applies offset voltage to v out set-point r/w l16s 0000h 0v 23h vout_cal_offset applies offset voltage to v out set-point r/w l16s 0000h 0v 24h vout_max sets maximum v out set-point r/w l16u n/a 1.15 x vset pin-strap setting 25h vout_margin_high sets v out set-point during margin high r/w l16u n/a 1.05 x vset pin-strap setting 26h vout_margin_low sets v out set-point during margin low r/w l16u n/a 0.95 x vset pin-strap setting 27h vout_transition_rate sets v out transition rate during margin commands r/w l11 ba00h 1v/ms 28h vout_droop sets v/i slope for total rail output current (all phases combined) r/w l11 n/a cfg pin-strap setting 33h frequency_switch sets switching frequency r/w l11 n/a sync pin-strap setting 37h interleave configures phase offset during group operation r/w bit n/a cfg pin-strap setting 38h iout_cal_gain sets impedance of current sense circuit r/w l11 b2aeh 0.67m 39h iout_cal_offset sets an offset to i out sense circuit r/w l11 bd00h -1.5a 40h vout_ov_fault_limit sets the v out overvoltage fault threshold r/w l16u n/a 1.10 x vset pin-strap setting 41h vout_ov_fault_response sets the v out overvoltage fault response r/ w bit 80h disable, no retry 44h vout_uv_fault_limit sets the v out undervoltage fault threshold r/w l16u n/a 0.85 x vset pin-strap setting 45h vout_uv_fault_response sets the v out undervoltage fault response r/w bit 80h disable, no retry 46h iout_oc_fault_limit sets the i out peak overcurrent fault threshold for each phase r/w l11 n/a cfg pin-strap setting 4bh iout_uc_fault_limit sets the i out valley undercurrent fault threshold for each phase r/w l11 n/a -1*iout_oc_fault_limit from cfg pin-strap setting 4fh ot_fault_limit sets the over-temperature fault limit r/w l11 ebe8h +125c 50h ot_fault_response sets the over-temperature fault response r/w bit bfh continuous retry, 280ms retry delay 51h ot_warn_limit sets the over-tempera ture warning limit r/w l11 eb70h +110c 52h ut_warn_limit sets the under-temper ature warning limit r/w l11 dc40h -30c
zl8802 fn8760 rev.3.00 page 23 of 91 nov 8, 2017 53h ut_fault_limit sets the under-temperature fault limit r/w l11 e530h -45c 54h ut_fault_response sets the under-temperature fault response r/w bit bfh continuous retry, 280ms retry delay 55h vin_ov_fault_limit sets the v in overvoltage fault threshold r/w l11 d380h 14v 56h vin_ov_fault_response sets the v in overvoltage fault response r/w bit 80h disable, no retry 57h vin_ov_warn_limit sets the v in overvoltage warning threshold r/w l11 d360h 13.5v 58h vin_uv_warn_limit sets the v in undervoltage warning threshold r/w l11 n/a 1.1 x uvlo pin-strap setting 59h vin_uv_fault_limit sets the v in undervoltage fault threshold r/w l11 n/a uvlo pin-strap setting 5ah vin_uv_fault_response sets the v in undervoltage fault response r/w bit bfh continuous retries, 280ms retry delay 5eh power_good_on sets the voltage threshold for power-good indication r/w l16u n/a 0.9 x vset pin-strap setting 60h ton_delay sets the delay time from enable to v out rise r/w l11 ca80h 5ms 61h ton_rise sets the rise time of v out after enable and ton_delay r/w l11 ca80h 5ms 64h toff_delay sets the delay time from disable to start of v out fall r/w l11 ca80h 5ms 65h toff_fall sets the fall time for vout after disable and toff_delay r/w l11 ca80h 5ms 78h status_byte first byte of status_word read bit 00h no faults 79h status_word summary of critical faults read bit 0000h no faults 7ah status_vout reports v out warnings/faults read bit 00h no faults 7bh status_iout reports i out warnings/faults read bit 00h no faults 7ch status_input reports input warnings/faults read bit 00h no faults 7dh status_temp reports temperature warnings/faults read bit 00h no faults 7eh status_cml reports communication, memory, logic errors read bit 00h no faults 80h status_mfr_specific reports voltage monitoring/clock synchronization faults read bit 00h no faults 88h read_vin reports input volt age measurement read l11 n/a n/a 89h read_iin reports input current measurement read l11 n/a n/a 8bh read_vout reports output voltage measurement read l16u n/a n/a 8ch read_iout reports output current measurement read l11 n/a n/a 8dh read_temperature_1 reports internal temperature measurement read l11 n/a n/a 8eh read_temperature_2 reports external temperature measurement from xtemp pins read l11 n/a n/a 8fh read_temperature_3 reports external temperature measurement from vmon/tmon pin. read l11 n/a n/a 94h read_duty_cycle reports actual duty cycle read l11 n/a n/a 95h read_frequency reports actual switching frequency read l11 n/a n/a 98h pmbus_revision reports th e pmbus revision used read bit 22h p1 r1.2, p2 r1.2 pmbus command summary (continued) code command name description type data format default value default setting
zl8802 fn8760 rev.3.00 page 24 of 91 nov 8, 2017 99h mfr_id sets a user defined identification r/w asc n/a 9ah mfr_model sets a user defined model r/w asc n/a 9bh mfr_revision sets a user defined revision r/w asc n/a 9ch mfr_location sets a user defined location identifier r/w asc n/a 9dh mfr_date sets a user defined date r/w asc n/a 9eh mfr_serial sets a user defined serialized identifier r/w asc n/a adh ic_device_id reports device identificati on information read cus 49a02d00h intersil zl8802 aeh ic_device_rev reports device revision information read cus 01000000h initial release b0h user_data_00 sets user defined data r/w asc n/a ceh min_vout_reg sets a minimum start-up voltage r/w l11 0000h 0mv d0h isense_config configures current sensing circuitry r/w bit 620eh downslope, 5 fault count, 384ns blanking, high range d1h user_config configures several user-level features r/w bit n/a set by cfg pin-strap setting d2h iin_cal_gain sets the resistance of the input current sensing resistor r/w l11 c200h 2m d3h ddc_config configures the ddc addressing and current sharing r/w bit n/a set by pin-strapped pmbus address and cfg pin-strap setting d4h power_good_delay sets the delay between pg threshold and pg assertion r/w l11 ba00h 1ms d5h multi_phase_ramp_gain adjusts the ramp-up and ramp-down rate by setting the feedback gain r/w cus 03h 3 d6h inductor sets the inductor value r/w l11 b133h 0.3h d7h snapshot_fault_mask masks faults that cause a snapshot to be taken r/w bit 0000h no faults masked d8h ovuv_config configures output voltage ov/uv fault detection r/w bit 00h low side fet off on fault, 1 violation triggers fault. d9h xtemp_scale calibrates external temperature sensor r/w l11 ba00h 1/degree c dah xtemp_offset offset calibration for external temperature sensor r/w l11 0000h no offset dbh mfr_smbalert_mask identifies which fault limits will not assert salrt r/w custom 00..00h n/a dch tempco_config sets tempco settings r/w bit 00h 0ppm/c ddh pinstrap_read_status reads pin-strap settings read bit n/a set by pin-straps dfh ascr_config configures the ascr settings r/w bit n/a ascrcfg pin-strap setting e0h sequence ddc rail sequencing configuration r/w bit 00h prequel and sequel disabled e1h track_config configures voltage tracking r/w bit 00h tracking disabled e2h ddc_group configures group id, fault spreading, operation, and v out r/w bit n/a set by cfg pin-strap e4h device_id returns the device identifier string read asc tbd zl8802, current revisions e5h mfr_iout_oc_fault_response configures the i out overcurrent fault response r/w bit 80h disable, no retry e6h mfr_iout_uc_fault_response configures the i out undercurrent fault response r/w bit 80h disable, no retry pmbus command summary (continued) code command name description type data format default value default setting
zl8802 fn8760 rev.3.00 page 25 of 91 nov 8, 2017 pmbus use guidelines the pmbus is a powerful tool that allows the user to optimize circuit performance by configur ing the zl8802 for their applicati on. when configuring the zl8802 in a circuit, the zl8802 should be disabled whenever most settings are ch anged with pmbus commands. some exceptions to this recommendation are operation, on_off_config, clear_faults, vout_command, vout_margin_high, vout_margin_low, and asccr_config. while the device is enabled any command can be read. many commands do not take effect until after the device has been reenabled, hence the recommendati on that commands that change device settings are written while the device is disabled. when sending the store_default_all, store_user_all, rest ore_default_all, and restor e_user_all commands, it is recommended that no other commands ar e sent to the device for 100ms after sending store or restore commands. in addition, there should be a 2ms delay between repeated read commands sent to the same device. when sending any other command, a 5ms delay is recommended between re peated commands sent to the same device. summary: all commands can be read at any time. always disable the zl8802 when writing commands that change device settings . exceptions to this rule are commands intended to b e written while the device is enable d, for example, vout_margin_high. to be sure a change to a device setting has taken effect, writ e the store_user_all command, th en cycle input power and reenable the device. e7h iout_avg_oc_fault_limit sets the i out average overcurrent fault threshold r/w l11 n/a set by cfg pin-strap e8h iout_avg_uc_fault_limit sets the i out average undercurrent fault threshold r/w l11 n/a -1* iout_avg_oc_fault_limit from cfg pin-strap setting e9h user_global_config sets options pertaining to advanced features r/w bit n/a set by cfg pin-strap setting eah snapshot 32-byte read-back of parametric and status values read bit n/a f0h legacy_fault_group configures fault group compatibility with older intersil digital power devices r/w bit 00000000h f3h snapshot_control snapshot feature control command r/w bit 00h n/a f4h restore_factory restores device to the hard-coded default values write n/a n/a n/a f5h mfr_vmon_ov_fault_limit sets the vmon overvoltage fault threshold r/w l11 c266h 2.4v, sps ot trip voltage f6h mfr_vmon_uv_fault_limit sets the vmon undervoltage fault threshold r/w l11 b0cch 0.2v, corresponds to -50c f7h mfr_read_vmon reads the vmon voltage read l11 n/a n/a f8h vmon_ov_fault_response configures the vmon overvoltage fault response r/w bit bfh continuous retry f9h vmon_uv_fault_response configures the vmon undervoltage fault response r/w bit bfh continuous retry fah security_level reports the security level read hex 01h public security level fbh private_password sets the private password string r/w asc 00?00h fch public_password sets the public password string r/w asc 00?00h fdh unprotect identifies which commands are protected r/w custom ff?ffh no commands are protected pmbus command summary (continued) code command name description type data format default value default setting
zl8802 fn8760 rev.3.00 page 26 of 91 nov 8, 2017 pmbus data formats linear-11 (l11) the l11 data format uses 5-bit two?s complement exponent (n) an d 11-bit two?s complement mantissa (y) to represent real world decimal value (x). relation between real world decimal value (x), n, and y is: x = y2 n linear-16 unsigned (l16u) the l16u data format uses a fixed exponent (hard-coded to n = -1 3h) and a 16-bit unsigned intege r mantissa (y) to represent rea l world decimal value (x). relation between real world decimal value (x), n, and y is: x = y2 -13 linear-16 signed (l16s) the l16s data format uses a fixed exponent (hard-coded to n = - 13h) and a 16-bit two?s complement mantissa (y) to represent rea l world decimal value (x). the relation between real world decimal value (x), n, and y is: x = y2 -13 bit field (bit) an explanation of bit field is provided in ? pmbus command detail ? starting on page 27 . custom (cus) an explanation of the custom data format is provided in ? pmbus command detail ? . a combination of bit field and integer are a common type of custom data format. ascii (asc) a variable length string of text ch aracters in the ascii data format. 76543210 76543210 data ? byte ? high data ? byte ? low exponent ? (n) mantissa ? (y)
zl8802 fn8760 rev.3.00 page 27 of 91 nov 8, 2017 pmbus command detail page (00h) definition: selects controller 0, controller 1, or both controllers 0 and 1 to receive comman ds. all commands following this command will be received and acted on by th e selected controller or controllers. data length in bytes: 1 data format: bit field type: r/w protectable: no default value: 00h (page 0) units: n/a command page (00h) format bit field bit position 76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value 00000000 bits 7:4 bits 3:0 page 0000 0000 0 0000 0001 1 1111 1111 both
zl8802 fn8760 rev.3.00 page 28 of 91 nov 8, 2017 operation (01h) definition: sets enable, disable, and v out margin settings. this command can also be monitored to read the operating state of the device on bits 7:6. writing immediate off will turn off the outp ut and ignore toff_delay and toff_fall settings. this command i s not stored like other pmbus commands. the value read reflects the current state of the device. when this command is written the command takes effect, but if a store _user_all written and the de vice is reenabled, the operatio n settings may not be the same settings that were written before the device was reenabled. paged or global: paged data length in bytes: 1 data format: bit field type: r/w protectable: yes default value: 00h (immediate off) units: n/a command operation (01h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 bits 7:6 bits 5:4 bits 3:0 (not used) unit on or off margin state 00 00 0000 immediate off (no sequencing) n/a 01 00 0000 soft off (with sequencing) n/a 10 00 0000 on nominal 10 01 0000 on margin low 10 10 0000 on margin high note: bit combinations not listed above may cause command errors.
zl8802 fn8760 rev.3.00 page 29 of 91 nov 8, 2017 on_off_config (02h) definition: configures the interpretation and coordination of the operat ion command and the enable pin (en). when bit 0 is set to 1 (turn off the output immediately), the toff_fall setting is ignored. paged or global: paged data length in bytes: 1 data format: bit field type: r/w protectable: yes default value: 17h (enable pin control, active high, turn off output immediately ? no ramp down) units: n/a clear_faults (03h) definition: clears all fault bits in all registers an d releases the salrt pin (if asserted) simu ltaneously. if a fault condition still exi sts, the bit will reassert immediately. this command will not restart a device if it has shut down, it will only clear the faults. paged or global: global data length in bytes: 0 byte data format: n/a type: write only protectable: yes default value: n/a units: n/a store_default_all (11h) definition: stores all current pmbus values from the operating memory into the nonvolatile default store memory. to clear the default store, perform a restore_factory then store_default_all. to add to the default store, perform a restore_default_all, write commands to be added, then store_default_all. this co mmand should not be used during device operation. the device will be unresponsive for 100ms while storing values. paged or global: global data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a command on_off_config (02h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00010111 bit number purpose bit value meaning 7:5 not used 000 not used 4:2 sets the default to ei ther operate any time power is present or for the on/off to be controlled by enable pin or operation command 000 not used 101 device starts from enable pin only. 110 device starts from operation command only. 1 (polarity of enable pin - not used) 1 active high only. 0 enable pin action when commanding the unit to turn off 0 use the configured ramp-down settings (?soft-off?). 1 turn off the output immediately.
zl8802 fn8760 rev.3.00 page 30 of 91 nov 8, 2017 restore_default_all (12h) definition: restores pmbus settings from the nonvolatile default store me mory into the operating memory. these settings are loaded during power-up if not superseded by settings in user store. se curity level is changed to level 1 following this command. this command should not be used during device operation. the devi ce will be unresponsive for 100ms while storing values. paged or global: global data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a store_user_all (15h) definition: stores all pmbus settings from the operat ing memory to the nonvolatile user st ore memory. to clear the user store, perform a restore_factory then store_user_all. to add to the user store, perform a restore_user_all, write commands to be added, then store_user_all. this comman d should not be used during device operation. the device will be unresponsive for 100ms while storing values. paged or global: global data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a restore_user_all (16h) definition: restores all pmbus settings from the user store memory to the operating me mory. command performed at power-up. security level is changed to level 1 following this command. this command should not be used during device operation. the devic e will be unresponsive for 100ms while restoring values. paged or global: global data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a vout_mode (20h) definition: reports the v out mode and provides the exponent used in calculating several v out settings. data length in bytes: 1 data format: bit type: read only default value: 13h (linear mode, exponent = -13) units: n/a command vout_mode (20h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00010011 mode bits 7:5 bits 4:0 (parameter) linear 000 5-bit two?s complement exponent for the mantissa delivered as the data bytes for an output voltage related command.
zl8802 fn8760 rev.3.00 page 31 of 91 nov 8, 2017 vout_command (21h) definition: sets or reports the target output voltage. the integer value is multiplied by 2 raised to the power of -13h. this command cannot be set to be higher than 115% of th e pin-strap vset setting, or vout_max if vout_max is set higher than 115% of the pin- strap vset setting. paged or global: paged data length in bytes: 2 data format: linear -16 unsigned type: r/w protectable: yes default value: vset pin-strap setting units: volts equation: v out = vout_command 2 -13 range : 0 to vout_max example : vout_command = 699ah = 27,034 target voltage equals 27034 2 -13 = 3.3v vout_trim (22h) definition: applies a fixed trim voltage to the output voltage command valu e. this command is typically us ed by the manufacturer of a power supply subassembly to calibrate a device in the subassembly circuit. the two bytes are formatted as a two?s complement bi nary mantissa, used in conjunction with the exponent of -13h. paged or global: paged data length in bytes: 2 data format: linear -16 signed type: r/w protectable: yes default value: 0000h units: volts equation: vout trim = vout_trim 2 -13 range : 150mv command vout_command (21h) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value vset pin-strap setting command vout_trim (22h) format linear-16 signed bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value0000000000000000
zl8802 fn8760 rev.3.00 page 32 of 91 nov 8, 2017 vout_cal_offset (23h) definition: applies a fixed offset voltage to the output voltage command value. this command is typically used to calibrate a device in the application circuit. the two bytes are fo rmatted as a two?s complement binary mant issa, used in conjunction with the expone nt of -13h. paged or global: paged data length in bytes: 2 data format: linear -16 signed type: r/w protectable: yes default value: 0000h units: volts equation: v out calibration offset = vout_cal_offset2 -13 range : 150mvv vout_max (24h) definition: sets an upper limit on the output voltage the unit can co mmand regardless of any other commands or combinations. the intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructi ve level rather than to be the primary output overprotection. if a vout_c ommand is sent with a value higher than vout_max, the device wi ll set the output voltage to vout_max. note that this command setting does not auto matically scale with a stored vout_command setting . paged or global: paged data length in bytes: 2 data format: linear -16 unsigned type: r/w protectable: yes default value: 1.15 x vset pin-strap setting units: volts equation: v out max = vout_max 2 -13 range : 0v to 5.5v command vout_cal_offset (23h) format linear-16 signed bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value0000000000000000 command vout_max (24h) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value 1.15 x vset pin-strap setting
zl8802 fn8760 rev.3.00 page 33 of 91 nov 8, 2017 vout_margin_high (25h) definition: sets the value of the v out during a margin high. this vout_margin_high command loads the unit with the voltage to which the output is to be changed when the operation command is set to ?margin high?. paged or global: paged data length in bytes: 2 data format: linear-16 unsigned type: r/w word protectable: yes default value: 1.05 x vset pin-strap setting units: v equation: v out margin high = vout_margin_high x 2 -13 range : 0v to vout_max vout_margin_low (26h) definition: sets the value of the v out during a margin low. this vout_margin_low co mmand loads the unit with the voltage to which the output is to be changed when the op eration command is set to ?margin low?. paged or global: paged data length in bytes: 2 data format: linear-16 unsigned type: r/w protectable: yes default value: 0.95 x vset pin-strap setting units: v equation: v out margin low = vout_margin_low range : 0v to vout_max command vout_margin_high (25h) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value 1.05 x vset pin-strap setting command vout_margin_low (26h) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value 0.95 x vset pin-strap setting
zl8802 fn8760 rev.3.00 page 34 of 91 nov 8, 2017 vout_transition_rate (27h) definition: sets the rate at which the output should change voltage wh en the device receives an op eration command (margin high, margin low) that causes the output voltage to change. the maxi mum possible positive value of the two data bytes indicates that the device should make the transition as quickl y as possible. this commanded rate does no t apply when the device is commanded to tu rn on or to turn off. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ba00h (1.0v/ms) units: v/ms equation: vout_transition_rate = y2 n range : 0.1 to 4v/ms vout_droop (28h) definition: sets the effective load line (v/i slope) for the rail in which the device is used. it is the ra te, in mv/a, at which the output voltage decreases with increasing output current for use with pa ssive current sharing schemes. fo r devices that are set to sink output current (negative output current) , the output voltage continues to increase as th e output current is negative. vout_droop is no t needed with a single (2-phase) zl8802. vout_droop is needed when multiple zl8802s are operated in current sharing mode, that is , 4-, 6-, and 8-phase configurations. in this case, vout_droop is ca lculated based on the combined output current of all phases a s applicable. paged or global: paged data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: set by cfg pin-strap setting units: mv/a equation: vout_droop = y2 n range : 0 to 40mv/a command vout_transition_rate (27h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1011101000000000 command vout_droop (28h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value set by cfg pin-strap setting
zl8802 fn8760 rev.3.00 page 35 of 91 nov 8, 2017 frequency_switch (33h) definition: sets the switching frequency of the device . initial default value is defined by a pin-strap and this value can be overridden by writing this command. if an external sync is utilized, this value should be set as close as possible to the external clock valu e. the output must be disabled when writing this command. available frequencies are defined by the equation f sw = 16mhz/n where 12 n 80. paged or global: global data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: sync pin-strap setting units: khz equation: frequency_switch = y2 n range : 200khz-1.33mhz interleave (37h) definition: configures the phase offset of a device that is sharing a comm on sync clock with other devices. a desired phase position is specified. interleave is used for setting the phase offset between individual devices, current sharing groups, and/or combinati ons of devices and current sharing groups. for de vices within single current sharing group the phase offset is set automatically. in a multiphase current share group the same inte rleave settings must be stored in all de vices in the current sharing group to phase spread properly . interleave offset refers to the phase offset of phase 0 of the device; phase 1 is always phase 0 + 180 degrees. interleave phase offset is calculated with equation 7 : phase offsets greater than 360 degrees are ?w rapped around? by subt racting 360 degrees. paged or global: paged data length in bytes: 2 data format: bit field type : r/w protectable: yes default value: set by cfg pin-strap setting. units: n/a command frequency_switch (33h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value sync pin-strapped value command interleave (37h) format bit field bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value set by cfg pin-strap setting bits purpose value description 15:8 not used 0 not used 7:4 number in group 0 to 15d sets the number of devices in the interleave group. a value of 0 is interpreted as 16. 3:0 position in group (interleave order) 0 to 15d sets position of the device?s ra il within the group. a value of 0 is interpreted as 16. position 1 will have a 22.5 degree offset. (eq. 7) phase offset (in degrees) rounded position 16 number ? ? ?? ?? 22.5 ? =
zl8802 fn8760 rev.3.00 page 36 of 91 nov 8, 2017 iout_cal_gain (38h) definition: sets the effective impedance across the current sense ci rcuit for use in calculating output current at +25c. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: b2aeh (0.67m ) units: m equation: iout_cal_gain = y2 n iout_cal_offset (39h) definition: used to null out any offsets in the output current sensing circuit, and to compensate for delayed measurements of current ramp due to the current sense blanking time (see ? isense_config (d0h) ? on page 62 ). paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: bd00h (-1.5a) units: a equation: iout_cal_offset = y2 n command iout_cal_gain (38h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1011001010101110 command iout_cal_offset (39h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1011110100000000
zl8802 fn8760 rev.3.00 page 37 of 91 nov 8, 2017 vout_ov_fault_limit (40h) definition: sets the v out overvoltage fault threshold. paged or global: paged data length in bytes: 2 data format: linear-16 unsigned type : r/w protectable: yes default value: 1.10 x vset pin-strap setting units: v equation: vout ov fault limit = vout_ov_fault_limit2 -13 range : 0v to 7.99v vout_ov_fault_response (41h) definition: configures the v out overvoltage fault response. the retry time is the time between restart attempts. paged or global: paged data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 80h (shut down immediately, no retries) units: retry time = 35ms increments command vout_ov_fault_limit (40h) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value 1.10 x vset pin-strap setting command vout_ov_fault_response (41h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bit field name value description 7:6 response behavior, the device: ?pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00-01 not used 10-11 disable and retry according to the setting in bits [5:3]. 5:3 retry setting 000 no retry. the output remains disa bled until the device is restarted. 001-110 not used 111 attempts to restart continuously, until it is commanded off (by the enable pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 38 of 91 nov 8, 2017 vout_uv_fault_limit (44h) definition: sets the v out undervoltage fault threshold. this fault is masked du ring ramp, before power-good is asserted or when the device is disabled. vout_uv_fault_limit sh ould be set to a value below power_good. paged or global: paged data length in bytes: 2 data format: linear-16 unsigned type : r/w protectable: yes default value: 0.85 x vset pin-strap setting units: v equation: v out uv fault limit = vout_uv_fault_limit2 -13 range : 0v to 7.99v vout_uv_fault_response (45h) definition: configures the v out undervoltage fault response. note that v out uv faults can only occur after power-good (pg) has been asserted. under some circumstances this will cause the output to stay fixed below the power-good threshold indefinitely. if thi s behavior is undesired, use setting 80h. the re try time is the time between restart attempts. paged or global: paged data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 80h (shut down immediately, no retries) units: retry time unit = 35ms command vout_uv_fault_limit (44h) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value 0.85 x vset pin-strap setting command vout_uv_fault_response (45h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bit field name value description 7:6 response behavior: the device: ? pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00-01 not used 10-11 disable and retry according to the setting in bits [5:3]. 5:3 retry setting 000 no retry. the output remains di sabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, until it is commanded off (by the enable pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 39 of 91 nov 8, 2017 iout_oc_fault_limit (46h) definition: sets the i out peak overcurrent fault threshold. this limit is applie d to current measurement samp les taken after the current sense blanking time has expired (see ? isense_config (d0h) ? on page 62 )). a fault occurs after this limit is exceeded for the number of consecutive samples as defined in isense_con fig. this feature shares the oc fault bit operation (in status_iout) and oc fault r esponse with iout_avg_oc_fault_limit. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: cfg pin-strap setting units: a equation: iout_oc_fault_limit = y2 n range : -100a to 100a iout_uc_fault_limit (4bh) definition: sets the i out valley undercurrent fault threshold. this limit is applied to current meas urement samples taken after the current sense blanking time has expired. a fault occurs after this limit is exceeded for the number of consecutive sample as defined in isense_config. this feature shares the uc fault bit operation (in status _iout) and uc fault response with iout_avg_uc_fault_lim it. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: -1 * iout_oc_fault_limit from cfg pin-strap setting units: a equation: iout_oc_fault_limit = y2 n range : -100a to 100a command iout_oc_fault_limit (46h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value cfg pin-strap setting command iout_uc_fault_limit (4bh) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value -1 * iout_oc_fault_ limit from cfg pin-strap setting
zl8802 fn8760 rev.3.00 page 40 of 91 nov 8, 2017 ot_fault_limit (4fh) definition: sets the temperature at which the device should indicate an over-temperature fault. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ebe8h (+125c) units: celsius equation: ot_fault_limit = y2 n range : 0 to 175c ot_fault_response (50h) definition: instructs the device on what action to take in response to an over-temperature fault. the retry time is the time between restart attempts. paged or global: paged data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: bfh (continuous retries, retry delay 280ms) units: retry time unit = 35ms command ot_fault_limit (4fh) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1110101111101000 command ot_fault_response (50h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10111111 bit field name value description 7:6 response behavior, the device: ?pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00-01 not used 10 disable and retry according to the setting in bits [5:3]. 11 output is disabled while the fault is present. operation resumes and the output is enabled when the temperature falls below the ot_warn_limit. 5:3 retry setting 000 no retry. the output remains di sabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, until it is commanded off (by the enable pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. a retry is attempted after the temperature falls below the ot_warn_limit. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 41 of 91 nov 8, 2017 ot_warn_limit (51h) definition: sets the temperature at which the device should indicate an over-temperature warning alarm. in response to the ot_warn_limit being exceeded, the device sets the temper ature bit in status_word, sets the ot_warning bit in status_temperature, and notifies the host. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: eb70h (+110c) units: celsius equation: ot_warn_limit = y2 n range : 0 to 175c ut_warn_limit (52h) definition: sets the temperature at which the device should indicate an under-temperature warning alarm. in response to the ut_warn_limit being exceeded, the device sets the temper ature bit in status_word, sets the ut_warning bit in status_temperature, and notifies the host. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: dc40h (-30c) units: celsius equation: ut_warn_limit = y2 n range : -55c to +25c command ot_warn_limit (51h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1110101101110000 command ut_warn_limit (52h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1101110001000000
zl8802 fn8760 rev.3.00 page 42 of 91 nov 8, 2017 ut_fault_limit (53h) definition: sets the temperature, in degrees celsius, of the unit at which it should indicate an under-temperature fault. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: e530h (-45c) units: celsius equation: ut_fault_limit = y2 n range : -55c to +25c ut_fault_response (54h) definition: configures the under-temperature fault response as defined by the table below. the retry time is the time between restart attempts. paged or global: paged data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: bfh (continuous retries, 280ms retry delay) units: retry time unit = 35ms command ut_fault_limit (53h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1110010100110000 command ut_fault_response (54h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10111111 bit field name value description 7:6 response behavior, the device: ?pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00-01 not used 10 disable and retry according to the setting in bits [5:3]. 11 output is disabled while the fault is present. operation resumes and the output is enabled when the temperature rises above the ut_warn_limit. 5:3 retry setting 000 no retry. the output remains disabled until the device is restarted. 001-110 not used 111 attempts to restart continuously, until it is commanded off (by the enable pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. a retry is attempted after the temperature rises above ut_warn_limit. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the ti me between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 43 of 91 nov 8, 2017 vin_ov_fault_limit (55h) definition: sets the v in overvoltage fault threshold. paged or global: global data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: d380h (14v) units: v equation: vin_ov_fault_limit = y2 n range : 0 to 19v vin_ov_fault_response (56h) definition: configures the v in overvoltage fault response as defined by the table below. paged or global: global data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 80h (disable, no retry) units: n/a command vin_ov_fault_limit (55h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1101001110000000 command vin_ov_fault_response (56h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bit field name value description 7:6 response behavior, the device: ?pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00-01 not used 10 disable and retry according to the setting in bits [5:3]. 11 output is disabled while the fault is present. operation resumes and the output is enabled when vin falls below the vin_ov_warn_limit. 5:3 retry setting 000 no retry. the output remains di sabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, until it is commanded off (by the enable pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. a retry is attempted after the output falls below the vin_ov_warn_limit. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 44 of 91 nov 8, 2017 vin_ov_warn_limit (57h) definition: sets the v in overvoltage warning threshold as defined by the ta ble below. in response to the ov_warn_limit being exceeded, the device sets the none of the above and input bits in status_word, sets the vin_ov_warning bit in status_input, and notifies the host. paged or global: global data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: d360h (13.5v) units: v equation: vin_ov_fault_limit = y2 n range : 0 to 19v vin_uv_warn_limit (58h) definition: sets the vin undervoltage warning threshold. if a vi n_uv_fault occurs, the input voltage must rise above vin_uv_warn_limit to clear the fault, which provides hysteresis to the fault threshold. in response to the uv_warn_limit being exceeded, the device sets the none of the above and input bits in status_word, sets the vin_uv_warning bit in status_input, and notifies the host. paged or global: global data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: 1.10 x uvlo pin-strap setting units: v equation: vin_uv_warn_limit = y2 n range : 0 to 19v command vin_ov_warn_limit (57h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1101001101100000 command vin_uv_warn_limit (58h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1.10 x uvlo pin-strap setting
zl8802 fn8760 rev.3.00 page 45 of 91 nov 8, 2017 vin_uv_fault_limit (59h) definition: sets the v in undervoltage fault threshold. paged or global: global data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: uvlo pin-strap setting units: v equation: vin_uv_fault_limit = y2 n range : 0 to 19v vin_uv_fault_response (5ah) definition: configures the vin undervoltage fault response as defined by the table below. the retry time is the time between restart attempts. paged or global: global data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: bfh (continuous retries, 280ms retry delay) units: retry time unit = 35ms command vin_uv_fault_limit (59h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value uvlo pin-strapped value command vin_uv_fault_response (5ah) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bit field name value description 7:6 response behavior, the device: ? pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00-01 not used 10 disable and retry according to the setting in bits [5:3]. 11 output is disabled while the fault is present. operation resumes and the output is enabled when v in rises above the vin_uv_warn_limit. 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, until it is commanded off (by the enable pin or operation command or both), bias power is removed, or an other fault condition causes the unit to shut down. a retry is attempted after the input voltag e rises above the vin_uv_warn_limit. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 46 of 91 nov 8, 2017 power_good_on (5eh) definition: sets the voltage threshold for power-good indication. power-good asserts when the output voltage exceeds power_good_on and deasserts when the outp ut voltage is less than vout_uv_fault_li mit. power_good_on should be set to a value above vout_uv_fault_limit. paged or global: paged data length in bytes: 2 data format: linear-16 unsigned type : r/w protectable: yes default value: 0.9 x vset pin-strap setting. units: v ton_delay (60h) definition: sets the delay time from when the device is enabled to the start of v out rise. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ca80h (5ms) units: ms equation: ton_delay = y2 n range : 0 to 5 seconds command power_good_on (5eh) format linear-16 unsigned bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default value 0.9 x vset pin-strap setting command ton_delay (60h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1 100101010000000
zl8802 fn8760 rev.3.00 page 47 of 91 nov 8, 2017 ton_rise (61h) definition: sets the rise time of vout after enable and ton_delay for single and dual channel operation. to adjust the rise time in 4-, 6- or 8-phase operation, us e multi_phase_ramp_gain (d5h). paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ca80h (5ms) units: ms equation: ton_rise = y2 n range : 0 to 100ms. although values can be set below 0.50ms, rise ti me accuracy cannot be guaranteed . in addition, short rise times may cause excessive input and output currents to flow , thus triggering overcurre nt faults at start-up. toff_delay (64h) definition: sets the delay time from disable to start of vout fall. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ca80h (5ms) units: ms equation: ton_delay = y2 n range : 0 to 5 seconds command ton_rise (61h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1 100101010000000 command toff_delay (64h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1 100101010000000
zl8802 fn8760 rev.3.00 page 48 of 91 nov 8, 2017 toff_fall (65h) definition: sets the fall time for v out after disable and toff_delay. this setting is only valid in single or 2-phase operation. setting the toff_fall to values less than 0.5ms will cause the zl8802 to tu rn-off both the high and low-side fets (or disable the drmos device) immediately after the expiration of the toff_delay time. in 4-, 6- or 8-phas e operation, the zl8802 will always turn-of f both the high and low-side fets (or disable the drmos device) immediately after the expiration of the toff_delay time. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ca80h (5ms) units: ms equation: toff_fall = y2 n range : 0 to 100ms. values less than 0.5ms will cause the zl8802 to tri- state the pwm signal (turn-off both the high and low-side fet s) immediately after the expiration of the toff_delay time. command toff_fall (65h) format linear-11 bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value 1 100101010000000
zl8802 fn8760 rev.3.00 page 49 of 91 nov 8, 2017 status_byte (78h) definition: returns two bytes of information with a summary of the unit?s fault condition. based on the information in these bytes, the host can get more information by reading th e appropriate status registers. the low byte of the status_word is the same register as the status_byte (78h) command. paged or global: paged data length in bytes: 2 data format: bit field type : read only protectable: no default value: 00h units: n/a command status_byte (78h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit number status bit name meaning 7 busy a fault was declared because the device was busy and unable to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature faul t or warning has occurred. 1 cml a communications, memory, or logic fault has occurred. 0 none of the above a fault other than the faults listed in bits 7:1 above has o ccurred. the source of the fault will be in bits 15:8 of the status_word
zl8802 fn8760 rev.3.00 page 50 of 91 nov 8, 2017 status_word (79h) definition: returns two bytes of information with a summary of the unit?s fault condition. based on the information in these bytes, the host can get more information by reading th e appropriate status registers. the low byte of the status_word is the same register as the status_byte (78h) command. paged or global: paged data length in bytes: 2 data format: bit field type : read only protectable: no default value: 0000h units: n/a command status_word (79h) format bit field bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function see following table default value 0000000000000000 bit number status bit name meaning 15 vout an output voltage fault or warning has occurred. 14 iout an output current fault has occurred. 13 input an input voltage fault or warning has occurred. 12 mfg_specific a manufacturer specific fault or warning has occurred. 11 power_good # the power_good signal, if present, is negated. ( note 15 ) 10 not used not used 9other a bit in status_vout, status_iout, status_input, status_temperature, status_cml, or status_mfr_specific is set. 8 not used not used 7busy a fault was declared because the device was busy and unable to respond. 6off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory, or logic fault has occurred. 0 none of the above a fault other than the faul ts listed in bits 7:1 above has occurred. the source of the fault will be in bits 15:8 of the status_word note: 15. if the power_good# bit is set, this indi cates that the power_good signal, if presen t, is signaling that the output power is not good.
zl8802 fn8760 rev.3.00 page 51 of 91 nov 8, 2017 status_vout (7ah) definition: returns one data byte with the status of the output voltage. paged or global: paged data length in bytes: 1 data format: bit field type : read only protectable: no default value: 00h units: n/a status_iout (7bh) definition: returns one data byte with the status of the output current. paged or global: paged data length in bytes: 1 data format: bit field type : read only protectable: no default value: 00h units: n/a command status_vout (7ah) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit number status bit name meaning 7 vout_ov_fault indicates an output overvoltage fault. 6 vout_ov_warning not used 5 vout_uv_warning not used 4 vout_uv_fault indicates an output undervoltage fault. 3:0 not used not used command status_iout (7bh) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit number status bit name meaning 7 iout_oc_fault an output overcurrent fault has occurred. 6 not used not used 5 not used not used 4 iout_uc_fault an output undercurrent fault has occurred. 3:0 not used not used
zl8802 fn8760 rev.3.00 page 52 of 91 nov 8, 2017 status_input (7ch) definition: returns input voltage and input current status information. paged or global: global data length in bytes: 1 data format: bit field type : read-only protectable: no default value: 00h units: n/a status_temperature (7dh) definition: returns one byte of information with a summary of any temperature related faults or warnings. paged or global: paged data length in bytes: 1 data format: bit field type : read-only protectable: no default value: 00h units: n/a command status_input (7ch) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit number status bit name meaning 7 vin_ov_fault an input overvoltage fault has occurred. 6 vin_ov_warning an input overvoltage warning has occurred. 5 vin_uv_warning an input undervoltage warning has occurred. 4 vin_uv_fault an input undervoltage fault has occurred. 3:0 not used not used command status_temp (7dh) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit number status bit name meaning 7 ot_fault an over-temperature fault has occurred. 6 ot_warning an over-temperature warning has occurred. 5 ut_warning an under-temperature warning has occurred. 4 ut_fault an under-temperature fault has occurred. 3:0 not used not used
zl8802 fn8760 rev.3.00 page 53 of 91 nov 8, 2017 status_cml (7eh) definition: returns one byte of information with a summary of any communications, logic, and/or memory errors. paged or global: global data length in bytes: 1 data format: bit field type : read only protectable: no default value: 00h units: n/a command status_cml (7eh) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 a packet error was detected in the pmbus command. 4:2 not used 1 a pmbus command tried to write to a read-only or protected comma nd, or a communication fault other than the ones listed in this table has occurred. 0not used
zl8802 fn8760 rev.3.00 page 54 of 91 nov 8, 2017 status_mfr_specific (80h) definition: returns one byte of information providing the status of the device?s voltage monitoring an d clock synchronization faults. paged or global: global data length in bytes: 1 data format: bit field type: read only protectable: no default value: 00h units: n/a read_vin (88h) definition: returns the input voltage reading. paged or global: global data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: v equation: read_vin = y2 n range : n/a command status_mfr_specific (80h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00000000 bit field name meaning 7not usednot used 6 ddc warning an error was detected on the ddc bus. 5 vmon uv warning the voltage on the vmon pin has dropped 10% below the level set by mfr_vmon_uv_fault. 4 vmon ov warning the voltage on the vmon pin has risen 10% above the level set by mfr_vmon_ov_fault. 3 external switching period fault loss of external clock synchronization has occurred. 2not usednot used 1 vmon uv fault the voltage on the vmon pin has dropped below the level set by mfr_vmon_uv_fault. 0 vmon ov fault the voltage on the vmon pin has risen above the level set by mfr_vmon_ov_fault. command read_vin (88h) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
zl8802 fn8760 rev.3.00 page 55 of 91 nov 8, 2017 read_iin (89h) definition: returns the input current reading. paged or global: global data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: a equation: read_iin = y2 n range : n/a read_vout (8bh) definition: returns the output voltage reading. paged or global: paged data length in bytes: 2 data format: linear-16 unsigned type: read only protectable: no default value: n/a equation: read_vout = read_vout 2 -13 units: v command read_iin (89h) format linear-11 bit position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a command read_vout (8bh) format linear-16 unsigned bit position1514131211109876543210 access rrrrrrrrrrrrrrrr default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
zl8802 fn8760 rev.3.00 page 56 of 91 nov 8, 2017 read_iout (8ch) definition: returns the output current reading. paged or global: paged data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: a equation: read_iout = y2 n range : n/a read_temperature_1 (8dh) definition: returns the temperature reading internal to the device. paged or global: global data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: c equation: read_temperature_1 = y2 n range : n/a command read_iout (8ch) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a command read_temperature_1 (8dh) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
zl8802 fn8760 rev.3.00 page 57 of 91 nov 8, 2017 read_temperature_2 (8eh) definition: returns the temperature reading from the external temperature device connected to xtemp. paged or global: paged data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: c equation: read_temperature_2 = y2 n range : n/a read_temperature_3 (8fh) definition: returns the temperature reading from the vmon/tmon pin when the device is configured to read temperature on the vmon/tmon pin by setting bit 12 in the user_global_config command to 1. the voltage on the vmon/tmon pin is converted to c by the equation tempertature 3 = (vmon voltage - 0.6v)/0.008. see mfr_vmon commands starting on page 85 (f5h, f6h, f8h, f9h) for fault limits when reading temper ature on the vmon/tmon pin. when using th e intersil isl9922x smart power stage, a 2:1 voltage divider is needed betwee n the tmon pin of the isl9922x an d the vmon/tmon pin of the zl8802. paged or global: global data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: c equation: read_temperature_3 = y2 n range : n/a command read_temperature_2 (8eh) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a command read_temperature_3 (8fh) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
zl8802 fn8760 rev.3.00 page 58 of 91 nov 8, 2017 read_duty_cycle (94h) definition : reports the actual duty cycle of the converter during the enable state. paged or global: paged data length in bytes: 2 data format: linear-11 type: read only protectable: no default value: n/a units: % equation: read_duty_cycle = y2 n range : 0 to 100% read_frequency (95h) definition : reports the actual switching frequency of the converter during the enable state. paged or global: global data length in bytes: 2 data format: linear-11 type: read only default value: n/a units: khz equation: read_frequency = y2 n range : n/a command read_duty_cycle (94h) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a command read_frequency (95h) format linear-11 bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
zl8802 fn8760 rev.3.00 page 59 of 91 nov 8, 2017 pmbus_revision (98h) definition: returns the revision of the pmbus specific ation to which the device is compliant. data length in bytes: 1 data format: bit field type: read only protectable : n/a default value: 22h (part 1 revision 1.2, part 2 revision 1.2) units: n/a mfr_id (99h) definition: sets a user defined identification string not to exceed 32 bytes. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_dat a_00 plus one byte per command cannot exceed 128bytes. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, w rite this command then pe rform a store/restore. paged or global: global data length in bytes: user defined data format: ascii, iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a mfr_model (9ah) definition: sets a user defined model string not to exceed 32byte s. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_dat a_00 plus one byte per command cannot exceed 128bytes. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, w rite this command then pe rform a store/restore. paged or global: global data length in bytes: user defined data format: ascii, iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a command pmbus_revision (98h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00100010 bits 7:4 part 1 revision bits 3:0 part 2 revision 0000 1.0 0000 1.0 0001 1.1 0001 1.1 0010 1.2 0010 1.2
zl8802 fn8760 rev.3.00 page 60 of 91 nov 8, 2017 mfr_revision (9bh) definition: sets a user defined revision string not to exceed 32byt es. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_dat a_00 plus one byte per command cannot exceed 128bytes. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, w rite this command then pe rform a store/restore. paged or global: global data length in bytes: user defined data format: ascii. iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a mfr_location (9ch) definition: sets a user defined location identifier string not to exceed 32bytes. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_dat a_00 plus one byte per command cannot exceed 128bytes. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, w rite this command then pe rform a store/restore. paged or global: global data length in bytes: user defined data format: ascii. iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a mfr_date (9dh) definition: sets a user defined date string not to exceed 32bytes. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and us er_data_00 plus one byte per command ca nnot exceed 128bytes . this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, write this comman d then perform a store/restore. paged or global: global data length in bytes: user defined data format: ascii. iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a mfr_serial (9eh) definition: sets a user defined serialized identifier string not to exce ed 32bytes. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_dat a_00 plus one byte per command cannot exceed 128bytes. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, w rite this command then pe rform a store/restore. paged or global: global data length in bytes: user defined data format: ascii. iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a
zl8802 fn8760 rev.3.00 page 61 of 91 nov 8, 2017 ic_device_id (adh) definition: reports device identification information. data length in bytes: 4 data format: cus type: block read protectable: no default value: 49a02d00h (zl8802) units: n/a ic_device_rev (aeh) definition: reports device revision information. data length in bytes: 4 data format: cus type: block read protectable: no default value: 01000000h (initial release) units: n/a user_data_00 (b0h) definition: sets a user defined data string not to exceed 32bytes. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and us er_data_00 plus one byte per command ca nnot exceed 128bytes . this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, write this comman d then perform a store/restore. paged or global: global data length in bytes: user defined data format: ascii. iso/iec 8859-1 type: block r/w protectable: yes default value: null units: n/a command ic_device_id (adh) format block read byte position 3210 function mfr code id high byte id low byte reserved default value 49h a0h 2ah 00h command ic_device_rev (aeh) format block read byte position 3210 function firmware major firmware minor factory configuration reserved default value 01h 00h 00h 00h
zl8802 fn8760 rev.3.00 page 62 of 91 nov 8, 2017 min_vout_reg (ceh) definition: sets the minimum output voltage in millivol ts (mv) that the device will attempt to regulate to during start-up and shutdown ramps. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: 0000h (0mv) units: a equation: min_vout_reg = y x 2 n isense_config (d0h) definition: configures current sense circuitry. paged or global: paged data length in bytes: 2 data format: bit field type: r/w word protectable: yes default value: 620eh (384ns blanking, sps sensing, high range) units: n/a range : n/a command min_vout_reg (ceh) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1111001001011000 command isense_config (d0h) format bit field bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value0110001000001110
zl8802 fn8760 rev.3.00 page 63 of 91 nov 8, 2017 bit field name value setting description 15:11 current sense blanking time 00000 0 sets the blanking time current sense blanking time in increments of 32ns 00001 32 00010 64 00011 96 00100 128 00101 160 00110 192 00111 224 01000 256 01001 288 01010 320 01011 352 01100 384 01101 416 01110 448 01111 480 10000 512 10001 544 10010 576 10011 608 10100 640 10101 672 10110 704 10111 736 11000 768 11001 800 11010 832 10:8 current sense fault count 000 1 sets the number of consecutive overcurre nt (oc) or undercurrent (uc) events required for a fault. an event can occur once during each switching cycle. for example, if 5 is selected, an oc or uc event must occur for 5 consecutive switching cycles, resulting in a dela y of at least 5 switching periods. 001 3 010 5 011 7 100 9 101 11 110 13 111 15 7:4 not used 0000 not used not used 3:2 current sense control 00 not used selection of current sensing method (sps imon) 01 dcr (down slope) 10 dcr (up slope) 11 sps 1:0 current sense range 00 low range low range 25mv, medium range 35mv, high range 50mv 01 medium range 10 high range 11 not used
zl8802 fn8760 rev.3.00 page 64 of 91 nov 8, 2017 user_config (d1h) definition: configures several user-level features. this command should be saved immediately after being written to the desired user or default store. this is recommended when written as an individual command or as part of a series of commands in a configuration file or script. paged or global: paged data length in bytes: 2 data format: bit field type: r/w protectable: yes default value: set by cfg pin-strap setting units: n/a command user_config (d1h) format bit field bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value cfg pin-strap setting bit field name value setting description 15:11 minimum duty cycle 00000 0-31d sets the minimum duty-cyc le to 2x(value+1)/512. must be enabled with bit 7 10 not used 1 not used not used 9:8 not used 00 not used not used 7 minimum duty cycle control 0 disable control for minimum duty cycle 1enable 6 not used 0 not used not used 5 vset select 0 vset0 0 = uses only vset0 to set the pin-strapped output voltage 1 vset1 1 = uses only vset1 to set the pin-strapped output voltage 4 not used 0 not used not used 3 pwml disabled state 0 low when disabled pwml is low (off) when device is disabled (bit 3 set to 0), or high (on) when device is disabled (bit 3 set to 1) 1 high when disabled 2 power-good configuration 0 open-drain 0 = pg is open-drain output 1 push-pull 1 = pg is push-pull output 1xtemp enable 0 disable enable external temperature sensor 1enable 0xtemp fault select 0 disable selects external temperature sensor to determine temperature faults 1enable
zl8802 fn8760 rev.3.00 page 65 of 91 nov 8, 2017 iin_cal_gain (d2h) definition: sets the effective impedance across the current sense circuit for use in calculating input current at +25c. paged or global: global data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: c200h (2m ) units: m equation: iin_cal_gain = y2 n ddc_config (d3h) definition: configures ddc addressing and current sharing for up to 8 phases . to operate as a 2-phase controller, set both phases to the same rail id, set phases in rail to 2, then set each phase id sequentially as 0 and 1. to operate as a 4-phase controller, set all phases to the same rail id, set phases in rail to 4, then set each phase id alternately, for example, the first zl8 802 will be set to 0 a nd 2, the second zl8802 will be set to 1 and 3. the zl8802 will automatically equally offset the phases in the rail. phase spreading is d one automatically as part of the ddc_config command. when using cfg pin-strap settings, the ddc_config command is set automatically. note: the output must be connected to vsen0p an d vsen0n when operating as a 2-phase controller. paged or global: paged data length in bytes: 2 data format: bit field type: r/w protectable: yes default value: pmbus address pin-strap dependent. units: n/a command iin_cal_gain (d2h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1100001000000000 command ddc_config (d3h) format bit field bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value000 lower 5 bits of device address 00000000 bit field name value setting description 15:13 phase id 0 to 7 0 sets the output 's phase position within the rail 12:8 rail id 0 to 31d 0 identifies the device as part of a current sharing rail (shared output) 7:3 not used 00 00 not used 2:0 phases in rail 0 to 7 0 identifies the nu mber of phases on the same rail (+1)
zl8802 fn8760 rev.3.00 page 66 of 91 nov 8, 2017 power_good_delay (d4h) definition: sets the delay applied between the output exceeding the pg threshold (power_good_on) an d asserting the pg pin. the delay time can range from 0ms up to 500ms, in steps of 125ns. a 1ms minimum configured value is recommended to apply proper debounce to this signal. paged or global: paged data length in bytes: 2 data format : linear-11 type: r/w protectable : yes default value: ba00h, 1ms units: ms equation: power_good_delay = y2 n range: 0 to 500ms multi_phase_ramp_gain (d5h) definition: indirectly determines the output voltage rise time during the turn-on ramp. typica l gain values range from 1 to 10. lower gain values produce longer ramp times. multi_phase_ramp_gain mode is automatically selected when the zls8802 is configured to operat e in a 4-phase current sharing group. when in multi_phase_ramp_gain mode, the turn-on ramp up is done with the high bandwidth ascr control circuitry disabled, resulting in a lower loop bandwidth during start-up ramps. afte r power_good has been asserted, as cr circuitry is enabled and th e zls8802 operates normally. when multi_phase_ramp_gain mode is enabled, soft-off ramps are not allowed (toff_fall is ignored). when the zl8802 is commanded to sh utdown, the pwmho/1 output is tri-stated, turning both the high-side and low-side mosfets off, and the pwml0/1 pin is pulled lo w (drmos disabled). large load current tr ansitions during multiphase ramp-ups will cause output voltage discontinuities. when the phase count is 2; that is, when the zl8802 is operat ing standalone, ascr is enabled at all times and all commands associated with turn-on and turn-off (ton_r ise, toff_fall, soft-off) operate normally. rise time can be calculated using equation 8 : paged or global: global data length in bytes: 1 data format: custom type : r/w protectable: yes default value: 03h units: n/a command power_good_delay (d4h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1011101000000000 command multi_phase_ramp_gain (d5h) format 1 byte binary bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w default value 00000011 bit field name value description 7:0 gain 00-ff start-up ramp gain (eq. 8) risetime vout_command 14 input voltage frequency_switch (in mhz) mul ti_phase_ramp_gain ? ? ? ? ? ? =
zl8802 fn8760 rev.3.00 page 67 of 91 nov 8, 2017 inductor (d6h) definition: informs the device of the circuit?s inductor value. this is used in adaptive algorithm calculat ions relating to the inductor ripple current. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: b133h (0.3h) units: h equation: inductor = y2 n range: 0 to 100h snapshot_fault_mask (d7h) definition: prevents faults from causing a snapsh ot event (and store) from occurring. data length in bytes: 2 data format: bit type: r/w protectable: yes default value: 0000h units: na range : na command inductor (d6h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1011000100110011 command snapshot_fault_mask (d7h) format bit field bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function see following table default value 0000000000000000 bit number status bit name meaning 15:14 not used not used 13 group ignore fault spreading faults 12 phase ignore other phase faults 11 cpu ignore cpu faults 10 crc ignore crc memory faults 9 not used not used 8 not used not used 7 iout_uc_fault ignore output undercurrent faults 6 iout_oc_fault ignore output overcurrent faults 5vin_uv_faultignore inpu t undervoltage faults 4 vin_ov_fault ignore inpu t undervoltage faults 3 ut_fault ignore under-temperature faults 2 ot_fault ignore over-temperature faults 1 vout_uv_fault ignore output undervoltage faults 0 vout_ov_fault ignore output overvoltage faults
zl8802 fn8760 rev.3.00 page 68 of 91 nov 8, 2017 ovuv_config (d8h) definition: configures the output voltage ov and uv fault detection feature paged or global: paged data length in bytes: 1 data format: bit field type: r/w protectable : yes default value: 00h units: n/a xtemp_scale (d9h) definition: sets a scalar value that is used for calibrating the external temperature. the constant is applied in the equation below to produce the read value of xtemp through the pmbus command read_temperature_2. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: ba00h (1.0) units: 1/c equation: range: 0.1 to 10 command ovuv_config (d8h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 bits purpose value description 7 controls how an ov fault response shutdown sets the output driver state 0 an ov fault does not enable low-side power device 1 an ov fault enables the low-side power device 6:4 not used 0 not used 3:0 defines the number of consecutive limit violations required to declare an ov or uv fault n n+1 consecutive ov or uv violations initiate a fault response command xtemp_scale (d9h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1011101000000000 et xtemp_offs e xtemp_scal 1 mperature externalte rature_2 read_tempe ? ? ? ? ? ? ? ? ? ? ?
zl8802 fn8760 rev.3.00 page 69 of 91 nov 8, 2017 xtemp_offset (dah) definition: sets an offset value that is used for calibrating the external temperature. the constant is a pplied in the equation below to produce the read value of xtemp through the pmbus command read_temperature_2. paged or global: paged data length in bytes: 2 data format: linear-11 type : r/w protectable: yes default value: 0000h (0) units: c equation: range: -100c to +100c command xtemp_offset (dah) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value0000000000000000 et xtemp_offs e xtemp_scal 1 mperature externalte rature_2 read_tempe ? ? ? ? ? ? ? ? ? ? ?
zl8802 fn8760 rev.3.00 page 70 of 91 nov 8, 2017 mfr_smbalert_mask (dbh) definition: used to prevent faults from acti vating the salrt pin. the bits in each byte co rrespond to a specific fault type as defined in the status command. data length in bytes: 7 data format: bit field type : r/w protectable: yes default value: 00 00 00 00 00 00 00h (no faults masked) units: n/a command mfr_smbalt_mask (dbh) format bit field access r/wr/wr/wr/wr/wr/wr/wr/w function see following table bit position 55 54 53 52 51 50 49 48 default value byte 6 00000000 bit position 47 46 45 44 43 42 41 40 default value byte 5 00000000 bit position 39 38 37 36 35 34 33 32 default value byte 4 00000000 bit position 31 30 29 28 27 26 25 24 default value byte 3 00000000 bit position 23 22 21 20 19 18 17 16 default value byte 2 00000000 bit position 15 14 13 12 11 10 9 8 default value byte 1 00000000 bit position 76543210 default value byte 0 00000000 byte status byte name meaning 6 status_mfr_specific mask manufacturer specific faul ts as identified in the status_mfr_specific byte. 5status_othernot used 4 status_cml mask communications, memory, or logic specific faults as identified in the status_cml byte. 3 status_temperature mask temperature specific faults as identified in the status_temperature byte. 2 status_input mask input specific faults as identified in the status_input byte. 1 status_iout mask output current specific faul ts as identified in the status_iout byte. 0 status_vout mask output voltage specific faul ts as identified in the status_vout byte.
zl8802 fn8760 rev.3.00 page 71 of 91 nov 8, 2017 tempco_config (dch) definition: configures the correction factor and temperature measuremen t source when performing temperature coefficient correction for current sense. tempco_config values are applied as negative correction to a positive temperature coefficient. tempco_config should be set to 3900ppm (27h) when using inductor dcr current se nsing to compensate for the vari ation in inductor resistance d ue to the temperature coefficient of copper. when using the isl9922x smart power stage, tempco_config should be set to 0ppm (00h) because the imon signal from the isl9922x is internally compensated for temperature. paged or global: paged data length in bytes: 1 data format: bit field type : r/w protectable: yes default value: 00h (0ppm/c, copper) equation: to determine the hex value of the tempco correction factor (tc) for current scale of a power stage current sensing, first determine the temperature coefficient of resistance for the sensing element, . this is found with equation 9 : where: r = sensing element resistance at temperature ?t? r ref = sensing element resistance at reference temperature t ref = temperature coefficient of resistance for the sensing element material t = temperature measured by temper ature sensor, in degrees celsius t ref = reference temperature that is specified at for the sensing element material after is determined, convert the value in units of 100ppm/ c. this value is then converted to a hex value with equation 10 : range : 0 to 12700ppm/ ? c command tempco_config (dch) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 bits purpose value description 7 selects the temp sensor source for tempco correction 0 selects the internal temperature sensor. 1 selects the xtemp pin for temperature measurements (2n3904 junction). note that xtemp must be enabled in user_config, bit 1. 6:0 sets the tempco correction in units of 100ppm/ ? c for iout_cal_gain tc rsen (dcr) = iout_cal_gain x (1+tc x (t-25)) where rsen = resistance of sense element. () ref ref ref rr rt t ? ? ? ? 6 10 100 tc ? ? ?
zl8802 fn8760 rev.3.00 page 72 of 91 nov 8, 2017 pinstrap_read_status (ddh) definition: reads back 7 bytes of 8-bit values that represent the pin-strap settings of each of the device ?s pin-strap pins. this value corresponds to a resistor value, a high, a low, or an open cond ition. the pin decode values correspond to pin-strap settings ac cording to table 9 : paged or global: global data length in bytes: 7 data format: bit field type: read only protectable: yes default value: pin-strap settings units: n/a table 9. pin decode values r (k ? )decode r (k ? )decode 10 00 51.1 11 11 01 56.2 12 12.1 02 61.9 13 13.3 03 68.1 14 14.7 04 75 15 16.2 05 82.5 16 17.8 06 90.9 17 19.6 07 100 18 21.5 08 110 19 23.7 09 121 1a 26.1 0a 133 1b 28.7 0b 147 1c 31.6 0c 162 1d 34.8 0d 178 1e 38.3 0e low f1 42.2 0f open f2 46.4 10 high f3 unmeasured f4 command read_pinstrap (ddh) format bit field bit position 55 54 53 52 51 50 49 48 access rrrrrrrr function ascrcfg pin decode default value ascrcfg pin-strap setting format bit field bit position 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 access rrrrrrrrrrrrrrrr function cfg pin decode sync pin decode default value cfg pin-strap setting sync pin-strap setting format bit field
zl8802 fn8760 rev.3.00 page 73 of 91 nov 8, 2017 bit position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 access rrrrrrrrrrrrrrrr function uvlo pin decode vset0 pin decode default value uvlo pin-strap setting vset0 pin-strap setting format bit field bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function vset1 pin decode reserved default value vset1 pin-strap setting n/a bits purpose value description 55:48 ascrcfg pin decode 00-f4h decode value of ascrcfg pin-strap setting. 47:40 cfg pin decode 00-f4h decode value of cfg pin-strap setting. 39:32 sync pin decode 00-f4h decode value of sync pin-strap setting. 31:24 uvlo pin decode 00-f4h decode value of uvlo pin-strap setting. 23:16 vset0 pin decode 00-f4h decode value of vset0 pin-strap setting. 15:8 vset1 pin decode 00-f4h decode value of vset1 pin-strap setting. 7:0 not used ff not used command read_pinstrap (ddh) (continued)
zl8802 fn8760 rev.3.00 page 74 of 91 nov 8, 2017 ascr_config (dfh) definition: allows user configuration of ascr settings. ascr gain an d residual value are automatically set by the zl8802 based on input voltage and output voltage. ascr gain is analogous to band width, ascr residual is analogou s to damping. to improve load transient response performance, increase ascr gain. to lower tr ansient response overshoot, increa se ascr residual. increasing a scr gain can result in increased pwm jitter and should be evaluated in the application circuit. excessive ascr gain can lead to exc essive output voltage ripple. increasing ascr residual to improve transi ent response damping can result in slower recovery times, but will not affect the peak output voltage deviation. typical ascr gain se ttings range from 100 to 1000, an d ascr residual settings range f rom 10 to 90. paged or global: paged data length in bytes: 4 data format: bit field and nonsigned binary type: r/w protectable: yes default value: ascrcfg pin-strap setting units: n/a command ascr_config (dfh) format bit field/linear-8 unsigned bit position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value00000001 ascrcfg pin-strap setting (residual) format linear-16 unsigned bit position1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value ascrcfg pin-strap setting (gain) bits purpose value description 31:25 not used 0000000h not used 24 ascr enable 1enable 0 disable 23:16 ascr residual setting 0 - 7fh ascr residual 15:0 ascr gain setting 0-ffh ascr gain
zl8802 fn8760 rev.3.00 page 75 of 91 nov 8, 2017 sequence (e0h) definition: identifies the rail ddc id of the prequel and sequel rails when performing multirail sequencing. the device will enable its output when its en or operation enable state, as defined by on_off_config, is set and the preq uel device has issued a power-goo d event on the ddc bus as a result of the prequel?s power-good (pg) signal going high. the device will disable its output (using the programmed delay values) when the sequel device has issued a powe r-down event on the ddc bus at the completion of its ramp-down (its output voltage is 0v). the data field is a two-byte value. the most-significant byte co ntains the 5-bit rail ddc id of the prequel device. the least-s ignificant byte contains the 5-bit rail ddc id of the sequel device. the most significant bit of each byte contains the enable of the preq uel or sequel mode. this command overrides the corresponding sequence configuration set by the config pin settings. paged or global: paged data length in bytes: 2 data format: bit field type: r/w protectable: yes default value: 00h (prequel and sequel disabled) units: n/a command sequence (e0h) format bit field bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value0000000000000000 bit field name value s etting description 15 prequel enable 0 disable disable, no prequel preceding this rail. 1 enable enable, prequel to this rail is defined by bits 12:8. 14:13 not used 0 not used not used 12:8 prequel rail ddc id 0-31d ddc id se t to the ddc id of the prequel rail. 7sequel enable 0 disable disable, no sequel following this rail. 1 enable enable, sequel to this rail is defined by bits 4:0. 6:5 not used 0 not used not used 4:0 sequel rail ddc id 0-31d ddc id set to the ddc id of the sequel rail.
zl8802 fn8760 rev.3.00 page 76 of 91 nov 8, 2017 track_config (e1h) definition: configures the voltage tracking modes of the device. single device (channel 0, channel 1 or 2-phase) tracking is supported. tracking as part of a 4-, 6- or 8-phase current sharing group is not supported. when tracking, the toff_delay in the tracking d evice must be greater than toff_delay + toff_fall in the device being tracked. when configured to track, vout_command must be set to the desired steady state output voltage. data length in bytes: 1 data format: bit field type: r/w protectable: yes default value: 00h units: n/a command track_config (e1h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 bit field name value setting description 7 voltage tracking control 0 disable tracking is disabled. 1 enable tracking is enabled. 6:3 not used 0000 not used not used 2 tracking ratio control 0 100% output tracks at 100% ratio of vtrk input. 1 50% output tracks at 50% ratio of vtrk input. 1 tracking upper limit 0 target voltage output voltage is limited by target voltage. 1 vtrk voltage output voltage is limited by vtrk voltage. 0 not used 0 not used not used
zl8802 fn8760 rev.3.00 page 77 of 91 nov 8, 2017 ddc_group (e2h) definition: rails (output voltages) are assigned group numbers to shar e specified behaviors. the ddc_group command configures fault spreading group id and enab le, broadcast operation group id and enable, an d broadcast vout_command group id and enable. note that ddc groups are separate and unique from ddc rail ids (see ? ddc_config (d3h) ? on page 65 ). current sharing rails need to be in the same ddc group to respond to broadcast vout_comma nd and operation commands. power fail event responses (and phases) are automatically spread in phase 0 and 1 when the zl8802 is operating in 2-phase current sharing mode when it is configured using ddc_config, regardless of its setting in ddc_group. paged or global: paged data length in bytes: 34 data format: bit field type: r/w protectable: yes default value: set by cfg pin-strap setting units: n/a command ddc_group (e2h) format bit field bit position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function not used en> vout_command group id default value set by cfg pin-strap setting format bit field bit position1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function not used en> operation group id not used en> power fail group id default value set by cfg pin-strap setting bits purpose value description 31:22 not used 00 not used 21 broadcast_vout_command response 1 responds to broadcast vout_c ommand with same group id. 0 ignores broadcast vout_command. 20:16 broadcast_vout_command group id 0-31d group id sent as data for broadcast vout_command events. 15:14 not used 00 not used 13 broadcast_operation response 1 responds to broadcast operation with same group id. 0 ignores broadcast operation. 12:8 broadcast_operation group id 0-31d group id sent as data for broadcast operation events. 7:6 not used 00 not used 5 power_fail response 1 responds to power_fail events with same group id by shutting down immediately. 0 responds to power_fail events with same group id with sequenced shutdown. 4:0 power_fail group id 0-31d group id sent as data for broadcas t power_fail events.
zl8802 fn8760 rev.3.00 page 78 of 91 nov 8, 2017 device_id (e4h) definition: returns the 16-byte (character) device identifier string. the fo rmat is: part number, major revi sion, (period), minor revision, engineering version letter paged or global: global data length in bytes: 16 data format: ascii. iso/iec 8859-1 type: block read protectable: read only default value: zl8802, current major revision, (period), current minor revision, current engineering version letter units: n/a mfr_iout_oc_fault_response (e5h) definition : configures the i out overcurrent fault response as defined by the tabl e below. the command format is the same as the pmbus standard fault responses exce pt that it sets the overcurrent status bit in status_iout. the retry time is the time betwee n restart attempts. paged or global: paged data length in bytes: 1 data format: bit field type: r/w protectable : yes default value: 80h (immediate shutdown, no retries) units: retry time unit = 35ms command device_id (e4h) format characters (bytes) characters1514131211109876543210 access rrrrrrrrrrrrrrrr function part number maj. rev. . min. rev engr. default valuezl8800 ****** * current revision at time of manufacture command mfr_iout_oc_fault_response (e5h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bit field name value description 7:6 response behavior, for all modes, the device: ? pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 not used 01 not used 10 disable without delay and retry acco rding to the setting in bits 5:3. 11 output is disabled while the fault is present. operation resumes and the output is enabled when the fault is no longer present. 5:3 retry setting 000 no retry. the output remains di sabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, without checking if the fault is still present, until it is commanded off (by the control pin or oper ation command or both), bias power is removed, or another fault condition causes th e unit to shut down. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets th e time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 79 of 91 nov 8, 2017 mfr_iout_uc_fault_response (e6h) definition: configures the i out undercurrent fault response as defined by the ta ble below. the command format is the same as the pmbus standard fault responses except that it sets the undercurrent status bit in stat us_iout. the retry time is the time betwe en restart attempts. data length in bytes: 1 paged or global: paged data format: bit field type: r/w protectable: yes default value: 80h (immediate shutdown, no retries) units: retry time unit = 35ms command mfr_iout_uc_fault_response (e6h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10000000 bit field name value description 7:6 response behavior, for all modes, the device: ? pulls salrt low ? sets the related fault bit in the status registers. fault bits ar e only cleared by the clear_faults command. 00 not used 01 not used 10 disable without delay and retry according to the setting in bits 5:3. 11 output is disabled while the fault is pr esent. operation resumes and the output is enabled when the fault is no longer present. 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, without checki ng if the fault is still present, until it is commanded off (by the control pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 80 of 91 nov 8, 2017 iout_avg_oc_fault_limit (e7h) definition: sets the i out average overcurrent fault threshold. for down-slope sens ing, this corresponds to the average of all the current samples taken during the (1-d) time interval, excluding the curren t sense blanking time (which oc curs at the beginning of the 1 -d interval). for up-slope sensing, this corresponds to the averag e of all the current samples take n during the d time interval, e xcluding the current sense blanking time (which occurs at the beginning of th e d interval). this feature shares the oc fault bit operation ( in status_iout) and oc fault response with iout_ oc_fault_limit. paged or global: paged data length in bytes: 2 data format: linear-11 type: r/w protectable : yes default value: cfg pin-strap setting units: amperes equation: iout_avg_oc_fault_limit = y2 n range : -100a to 100a iout_avg_uc_fault_limit (e8h) definition: sets the i out average undercurrent fault threshold. for down-slope sens ing, this corresponds to the average of all the current samples taken during the (1-d) time interval, excluding the curren t sense blanking time (which oc curs at the beginning of the 1 -d interval). for up-slope sensing, this corresponds to the averag e of all the current samples take n during the d time interval, e xcluding the current sense blanking time (which occurs at the beginning of th e d interval). this feature shar es the uc fault bit operation ( in status_iout) and uc fault respon se with iout_ uc_fault_limit. paged or global: paged data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: -1 x iout_avg_oc_fault_ limit as set by cfg pin-strap setting units: amperes equation: iout_avg_uc_fault_limit = y2 n range : -100a to 100a command iout_avg_oc_fault_limit (e7h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value cfg pin-strap setting command iout_avg_uc_fault_limit (e8h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value -1 x iout_avg_oc_fault_li mit as set by cfg pin-strap setting
zl8802 fn8760 rev.3.00 page 81 of 91 nov 8, 2017 user_global_config (e9h) definition: used to set options for output voltage sensing, vmon/tmon pin configuration, smbus time-o ut, and ddc and sync output configurations. paged or global: global data length in bytes: 2 data format: bit field type: r/w protectable: yes default value: set by cfg pin-strap setting units: n/a command user_global_config (e9h) format bit field bit position1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value set by cfg pin-strap setting bits purpose value description 15:13 not used 000000 not used 12 vmon/tmon config 0 mfr_read_vmon returns volt age on vmon pin in volts. external 16:1 voltage divider needed on vmon/tmon pin (pin 6) to voltage being monitored. 1 read_temperature_3 returns tmon in c. external 2:1 voltage divider needed on vmon/tmon pin (pin 6) to sps tmon pin. 11:10 not used 00 not used 9:8 vsense select for monitoring and fault detection 00 output 0 uses vsen0, output 1 uses vsen1 01 both outputs use vsen0 10-11 not used 7 not used 0 not used 6 ddc output configuration 0 ddc output open-drain 1 ddc output push-pull 5 not used 0 not used 4 disable smbus time-outs 0 smbus time-outs enabled 1 smbus time-outs disabled 3 not used 0 not used 2:1 sync i/o control 00 use internal clock (frequency initially set with pin-strap) 01 use internal clock and output intern al clock (not for use with pin-strap) 10 use external clock 11 not used 0 not used 0 not used
zl8802 fn8760 rev.3.00 page 82 of 91 nov 8, 2017 snapshot (eah) definition: a 32-byte read-back of parametric and status values. it allows mo nitoring and status data to be stored to flash either during a fault condition or through a system-defin ed time using the snapshot_control command. snapshot is continuously updated in ram and can be read using the snapshot comm and. when a fault occurs, the latest snapshot in ram is stored to flash. snapshot data can read back by writing a 01h to the snapshot_control command, then reading snapshot. paged or global: paged data length in bytes: 32 data format: bit field type: block read protectable: no default value: n/a units: n/a byte number value pmbus command format 31:23 not used not used 0000h 22 flash memory status byte n/a bit field 21 manufacturer specific status byte status_mfr_specific (80h) 1 byte bit field 20 cml status byte status_cml (7eh) 1 byte bit field 19 temperature status byte status_temperature (7dh) 1 byte bit field 18 input status byte status_input (7ch) 1 byte bit field 17 i out status byte status_iout (7bh) 1 byte bit field 16 v out status byte status_vout (7ah) 1 byte bit field 15:14 switching frequency read_frequency (95h) 2 byte linear-11 13:12 external temperature read_temperature_2 (8eh) 2 byte linear-11 11:10 internal temperature read_temperature_1 (8dh) 2 byte linear-11 9:8 duty cycle read_duty_cycle (94h) 2 byte linear-11 7:6 highest measured output current n/a 2 byte linear-11 5:4 output current read_iout (8ch) 2 byte linear-11 3:2 output voltage read_vout (8bh) 2 byte linear-16 unsigned 1:0 input voltage read_vin (88h) 2 byte linear-11
zl8802 fn8760 rev.3.00 page 83 of 91 nov 8, 2017 legacy_fault_group (f0h) definition: allows the zl8802 to sequence and fault spread with devices other than the zl8800 family of ics. this command sets which rail ddc ids should be listened to for fault spreading information. the data se nt is a 4-byte, 32-bit bit vector where ev ery bit represents a rail?s ddc id. a bit set to 1 indicates a device ddc id to which the configured device will respond upon receiving a fault spreading event. in this vector, bit 0 of byte 0 corresponds to the rail with ddc id 0. following through, bit 7 of byte 3 corr esponds to the rail with ddc id 31. note: the device/rail?s own ddc id shou ld not be set within the legacy_fault_group command for that device/rail. all devices in a current share rail (devices other than the zl8800 family ics) must shut down for the rail to report a shutdown . if fault spread mode is enabled in user_config, the device will immediately shut down if on of its ddc_group members fail. the device/rail will attempt its configured restart only after all devices/rails within the ddc_group have cleared their faults. if fault spread mode is disabled in user_config, the device will perform a sequenced shutdown as defined by the sequence command setting. the rails/devices in a sequencing set only atte mpt their configured restart afte r all faults have cleared with in the ddc_group. if fault spread mode is disabled and sequencing is al so disabled, the device will ignore faults from other devices a nd stay enabled. paged or global: paged data length in bytes: 4 data format: bit field type: block r/w protectable: yes default value: 00000000h units: n/a command legacy_fault_group (f0h) format bit field bit position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value0000000000000000 format bit field bit position1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function see following table default value0000000000000000 bit field name value setting description 31:0 fault group na 00000000h identifies the devices in the fault spreading group.
zl8802 fn8760 rev.3.00 page 84 of 91 nov 8, 2017 snapshot_control (f3h) definition: writing a 01h will cause the device to copy the current sn apshot values from nvram to the 32-byte snapshot command parameter. writing a 02h will cause the device to write the curren t snapshot values to nvram, 03h will erase all snapshot value s from nvram. write (02h) and erase (03h) can only be used when th e device is disabled. all other values will be ignored. snapsho t 03h must be written to the device when the device is disabled. data will not be updated, or written to nvram after a fault occu rs until the snapshot 03h command has been written. paged or global: paged data length in bytes: 1 data format: bit field type: r/w byte protectable: yes default value: 00h units: n/a restore_factory (f4h) definition: restores the device to the hard-coded factory default values and pin-strap definitions. the device retains the default and user stores for restoring. security level is changed to level 1 following this command. paged or global: global data length in bytes: 0 data format: n/a type: write only protectable: yes default value: n/a units: n/a command snapshot_control (f3h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 value description 01 read snapshot values from nvram 02 write snapshot values to nvram 03 erase snapshot values from nvram
zl8802 fn8760 rev.3.00 page 85 of 91 nov 8, 2017 mfr_vmon_ov_fault_limit (f5h) definition: sets the vmon over-temperature fault threshold. the vmon over voltage warn limit is automatica lly set to 90% of this fault value. if vmon is not used, set vmon_ov_fault_response to 00h, which will disable vmon ov faults entirely. paged or global: global data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: c266h (2.4v) units: volts equation: mfr_vmon_ov_fault_limit = y2 n range : 0 to 20v mfr_vmon_uv_fault_limit (f6h) definition: sets the vmon undervoltage fault threshold. the vmon undervol tage warn limit is automatically set to 110% of this fault value. if vmon is not used, set vmon_uv_fault_response to 00h, which will disable vmon uv faults entirely. paged or global: global data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: b0cch (0.2v) units: volts equation: mfr_vmon_uv_fault_limit = y x 2 n range : 0 to 20v command mfr_vmon_ov_fault_limit (f5h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1110001001100110 command mfr_vmon_uv_fault_limit (f6h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value1011000011001100
zl8802 fn8760 rev.3.00 page 86 of 91 nov 8, 2017 mfr_read_vmon (f7h) definition: reads the voltage on the vmon pin. paged or global: global data length in bytes: 2 data format: linear-11 type: r/w protectable: no default value: n/a units: c equation: mfr_read_vmon = y x 2 n range : -200c to +200c vmon_ov_fault_response (f8h) definition: configures the vmon overvoltage fault resp onse as defined by the table below. no te: the retry time is the time between restart attempts. if vmon is not used, set this respon se to 00h, which will disable vmon ov faults entirely. paged or global: global data length in bytes: 1 data format: bit field type: r/w protectable: yes default value: bfh (continuous retries) units: n/a command mfr_read_vmon (f7h) format linear-11 bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function signed exponent, n signed mantissa, y default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a command vmon_ov_fault_response (f8h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10111111 bit field name value description 7:6 response behavior, the device: ? pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 ignore faults 01 not used 10 disable without delay and retry according to the setting in bits 5:3. 11 output is disabled while the fa ult is present. operation resu mes and the output is enabled when vmon falls below 95% of the vmon_ov_faul t_limit setting. 5:3 retry setting 000 no retry. the output remains di sabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, without checking if the fault is still present, until it is commanded off (by the control pin or oper ation command or both), bias power is removed, or another fault condition causes the unit to shut down. a retry is attempted after vmon falls below 95% of the vmon_ov_fault_li mit. the time between the start of each attempt to restart is set by the valu e in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 87 of 91 nov 8, 2017 vmon_uv_fault_response (f9h) definition: configures the vmon undervoltage fault re sponse as defined by the table below. no te: the retry time is the time between restart attempts. if vmon is not used, set this respon se to 00h, which will disable vmon uv faults entirely. paged or global: global data length in bytes: 1 data format: bit field type: r/w protectable: yes default value: bfh (continuous retries) units: retry time unit = 35ms security_level (fah) definition: the device provides write protection for individual commands. each bit in the unprotect parameter controls whether its corresponding command is writable (commands are always readable). if a command is not writable, a password must be entered to change its parameter (that is, to enable writ es to that command). passwords can be eith er public or private. the public passwor d provides a simple lock-and-key protection against a ccidental changes to the device. it would ty pically be sent to the device in the appl ication before making changes. private passwords allow commands marked as no nwritable in the unprotect parameter to be changed. private passwords are intended for protecting defaul t-installed configurations and would not ty pically be used in the application. each store (user and default) can have its own unprotect string and private pass word. if a command is marked as nonwritable in the default unprotect parameter (its corresponding bit is cleared), the private password in the defa ult store must be sent to change that command. if a command is writable accordin g to the default unprotect parameter, it ma y still be marked as nonwritable in the us er store unprotect parameter. in this case, the user privat e password can be sent to make the command writable. the device supports four levels of security. each level is designed to be used by a particular class of users, ranging from mod ule manufacturers to end users, as discussed below. levels 0 and 1 correspond to the public password. all other levels require a pr ivate password. writing a private password can only raise the security level. writing a public password will reset the level down to 0 or 1. figure 12 on page 88 shows the algorithm used by the device to dete rmine if a particular command write is allowed. paged or global: global data length in bytes: 1 data format: hex type: read byte protectable: no default value: 01h units: n/a command vmon_uv_fault_response (f9h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 10111111 bit field name value description 7:6 response behavior, the device: ? pulls salrt low ? sets the related fault bit in the status registers. fault bits are only cleared by the clear_faults command. 00 fault ignored 01 not used 10 disable without delay and retry acco rding to the setting in bits 5:3. 11 output is disabled while the fault is present. operation resumes and the output is enabled when vmon rises above 105% of the vmon_uv_fault_limit setting. 5:3 retry setting 000 no retry. the output remains di sabled until the fault is cleared. 001-110 not used 111 attempts to restart continuously, without checking if the fault is still present, until it is commanded off (by the control pin or oper ation command or both), bias power is removed, or another fault condition causes the unit to shut down. a retry is attempted after vmon has risen above 105% of vmon_uv_faul t_limit. the time between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms. 2:0 retry delay 000-111 retry delay time = (value +1)*35ms. sets th e time between retries in 35ms increments. range is 35ms to 280ms.
zl8802 fn8760 rev.3.00 page 88 of 91 nov 8, 2017 security level 3 ? module vendor level 3 is intended primarily for use by module vendors to protect device configurations in the default store. clearing a unpro tect bit in the default store implies that a command is writable only at level 3 and above. the device?s security level is raised to lev el 3 by writing the private password value previously stored in the defaul t store. to be effective, the module vendor must clear the un protect bit corresponding to the store_default_all and restore_default co mmands. otherwise, level 3 protection is ineffective because the entire store could be replaced by the user, including the enclosed private password. always writeable ? security level == 3 ? default unprotect == 0 ? security level == 2 ? user unprotect == 0 ? security level == 1 ? n n n n write allowed write prohibited y y y y write attempted read only ? n n y y y n figure 12. algorithm to determine when a command is writable
zl8802 fn8760 rev.3.00 page 89 of 91 nov 8, 2017 security level 2 ? user level 2 is intended for use by the end user of the device. clearing a unprotect bit in the user store implies that a command is writable only at level 2 and above. the device?s security level is rais ed to level 2 by writing the private password value previously st ored in the user store. to be effective, the user must clear the unprotec t bit corresponding to the store_user_all, restore_default_all, store_default_all, and restore_default comm ands. otherwise, level 2 protection is ineffective because the entire store could be replaced, including the enclosed private password. security level 1 ? public level 1 is intended to protect against accidental changes to ordi nary commands by providing a gl obal write-enable. it can be us ed to protect the device from erroneous bus operat ions. it provides access to commands whose unprotect bit is set in both the default and user store. security is raised to level 1 by writing the public password stored in the user store using the public_password com mand. the public password stored in the default store has no effect. security level 0 - unprotected level 0 implies that only commands which ar e always writable (e.g., public_password) ar e available. this represents the lowest authority level and hence the most protected state of the device. the level can be reduced to 0 by using public_password to wri te any value which does not match the stored public password. private_password (fbh) definition: sets the private password string. paged or global: global data length in bytes: 9 data format: ascii. iso/iec 8859-1 type: block r/w protectable: no default value: 000000000000000000h units: n/a public_password (fch) definition : sets the public password string. paged or global: global data length in bytes: 4 data format: ascii. iso/iec 8859-1 type: block r/w protectable: no default value: 00000000h units: n/a unprotect (fdh) definition: sets a 256-bit (32-byte) parameter which identifies which co mmands are to be protected against write-access at lower security levels. each bit in this parameter corresponds to a co mmand according to the command?s code. the command with a code o f 00h (page) is protected by the least-significant bit of the leas t-significant byte, followed by the command with a code of 01h and so forth. note that all possible commands have a corresponding bit regardless of whether they are protectable or supported by the device. clearing a command?s unprotect bit indicates that write-access to that command is only allowed if the device?s security level h as been raised to an appropriate level. the unprotect bits in the default store require a security level 3 or greater to be writab le. the unprotect bits in the user store require a security level of 2 or higher. data length in bytes: 32 paged or global: global data format: custom type: block r/w protectable: no default value: ff?ffh units: n/a
zl8802 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html fn8760 rev.3.00 page 90 of 91 nov 8, 2017 ? copyright intersil americas llc 2015-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary . you can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please visi t our website to make sure you have the latest revision. date revision change nov 8, 2017 fn8760.3 changed all sps references from isl99227 to isl99227b. added an explanation of the en0 and en1 timing rest rictions to ?enable pin operation and timing? on page 16. updated to the current renesas format. may 25, 2017 fn8760.2 changed isl99226 to isl99227 in figure 1 on page 3. added related literature section. updated disclaimer. dec 11, 2015 fn8760.1 added junction temperature to the ?thermal information? on page 8. added zl8802alaft7a to the ordering information table on page 7. aug 6, 2015 fn8760.0 initial release
zl8802 fn8760 rev.3.00 page 91 of 91 nov 8, 2017 package outline drawing l44.7x7b 44 lead quad flat no-lead plastic package rev 0, 10/09 7.00 a b 7.00 (4x) 0.15 6 pin 1 index area located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0.2 ref 0 . 05 max. 0 . 00 min. 5 34 pin #1 44 5.00 typ 40x 0.50 exp. dap 11 1 33 22 44x 0.55 0.1 12 6 ( 44 x 0.75) (44x .25) ( 40x 0.50) ( 6.65 ) ( 5.20) 5.20 0.1 exp. dap 0.10 44x 0.25 a mc b 4 5.20 0.1 1.00 max see detail "x" 0.08 0.10 c c c ( 6.65 ) ( 5.20 ) 23 index area side view complies to jedec mo220 vkkd-1. 7. for the most recent package outline drawing, see l44.7x7b .

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